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Graphics Controller Hardware Specifications
Revision 2.0b 23 May 2000
MB86290A
Copyright (c) FUJITSU LIMITED 1998, 1999
ALL RIGHTS RESERVED
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All Rights Reserved
The information in this document has been carefully checked and is believed to be reliable. However, Fujitsu Limited assumes no responsibility for inaccuracies. The information in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu Limited, or its subsidiaries. Fujitsu Limited reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu Limited.
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Overview.................................................................................................................................7 1.1 Introduction .....................................................................................................................7 1.2 System Configuration .....................................................................................................8 1.3 Outline ............................................................................................................................9 1.4 Block Diagram ..............................................................................................................10 1.5 Functional Overview ..................................................................................................... 11 1.5.1 System Configuration ........................................................................................................ 11 1.5.2 Display Controller ..............................................................................................................12 1.5.3 Frame Control ....................................................................................................................13 1.5.4 2D Drawing ........................................................................................................................14 1.5.5 3D Drawing ........................................................................................................................16 1.5.6 Special Effects ...................................................................................................................17 1.5.7 Display List.........................................................................................................................19 2 Signal Pins............................................................................................................................20 2.1 Signals ..........................................................................................................................20 2.1.1 Signals ...............................................................................................................................20 2.2 Pin Assignment.............................................................................................................21 2.2.1 Pin Assignment Diagram ...................................................................................................21 2.2.2 Pin Assignment Table ........................................................................................................22 2.3 Signal Descriptions .......................................................................................................24 2.3.1 Host CPU Interface............................................................................................................24 2.3.2 Video Interface...................................................................................................................26 2.3.3 Graphics Memory Interface ...............................................................................................28 2.3.4 Clock Input .........................................................................................................................29 3 Host Interface .......................................................................................................................30 3.1 Operation Mode ............................................................................................................30 3.1.1 Host CPU Mode .................................................................................................................30 3.1.2 Endian................................................................................................................................30 3.2 Access Mode ................................................................................................................31 3.2.1 SRAM Interface .................................................................................................................31 3.2.2 FIFO Interface....................................................................................................................31 3.3 DMA Transfer ...............................................................................................................32 3.3.1 Data Transfer Unit..............................................................................................................32 3.3.2 Address Mode....................................................................................................................32 3.3.3 Bus Mode...........................................................................................................................33 3.3.4 DMA Transfer Request ......................................................................................................33 3.3.5 Ending DMA Transfer ........................................................................................................34 3.4 Interrupt Request ..........................................................................................................35 3.5 Transfer of Local Display List .......................................................................................36 3.6 Memory Map.................................................................................................................37 4 Graphics Memory .................................................................................................................38 4.1 Configuration ................................................................................................................38 4.1.1 Data Type...........................................................................................................................38 4.1.2 Memory Layout ..................................................................................................................39 4.1.3 Memory Data Format.........................................................................................................40
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4.2 Frame Management .....................................................................................................42 4.2.1 Single Buffer ......................................................................................................................42 4.2.2 Double Buffer .....................................................................................................................42 4.3 Memory Access ............................................................................................................43 4.3.1 Memory Access by Host CPU ...........................................................................................43 4.3.2 Priority of Memory Access .................................................................................................43 5 Display Controller .................................................................................................................44 5.1 Overview.......................................................................................................................44 5.2 Display Function ...........................................................................................................45 5.2.1 Layer Configuration ...........................................................................................................45 5.2.2 Overlay...............................................................................................................................46 5.2.3 Display Parameters ...........................................................................................................47 5.2.4 Display Position Control.....................................................................................................48 5.3 Display Color ................................................................................................................50 5.3.1 Color Look-up Table...........................................................................................................50 5.3.2 Chroma-key Operation ......................................................................................................50 5.4 Cursor ...........................................................................................................................51 5.4.1 Cursor Display Function ....................................................................................................51 5.4.2 Cursor Management ..........................................................................................................51 5.5 Processing Flow for Display Data.................................................................................52 5.6 Synchronization Control ...............................................................................................54 5.6.1 Applicable Display Resolution ...........................................................................................54 5.6.2 Interlace Display ................................................................................................................54 5.6.3 External Synchronization ...................................................................................................55 5.7 Video Interface..............................................................................................................58 5.7.1 NTSC Output .....................................................................................................................58 6 Drawing Control ....................................................................................................................59 6.1 Coordinates ..................................................................................................................59 6.1.1 Drawing Coordinate ...........................................................................................................59 6.1.2 Texture Coordinate ............................................................................................................60 6.1.3 Frame Buffer ......................................................................................................................61 6.2 Polygon Drawing...........................................................................................................62 6.2.1 Drawing Primitives .............................................................................................................62 6.2.2 Polygon Drawing................................................................................................................62 6.2.3 Drawing Parameters ..........................................................................................................63 6.2.4 Anti-aliasing Function ........................................................................................................64 6.3 Bit Map Operation.........................................................................................................65 6.3.1 BLT.....................................................................................................................................65 6.3.2 Pattern Data Format ..........................................................................................................65 6.4 Texture Mapping ...........................................................................................................66 6.4.1 Texture Size .......................................................................................................................66 6.4.2 Texture Memory .................................................................................................................66 6.4.3 Texture Lapping .................................................................................................................67 6.4.4 Filtering ..............................................................................................................................68 6.4.5 Perspective Correction ......................................................................................................69 6.4.6 Texture Blending ................................................................................................................69 6.5 Rendering .....................................................................................................................70
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6.5.1 Tiling...................................................................................................................................70 6.5.2 Alpha Blending...................................................................................................................71 6.5.3 Logical Calculation.............................................................................................................71 6.5.4 Hidden Surface Management ............................................................................................72 6.6 Drawing Attributes ........................................................................................................73 6.6.1 Line Draw Attributes ..........................................................................................................73 6.6.2 Triangle Draw Attributes ....................................................................................................73 6.6.3 Texture Attributes ...............................................................................................................74 6.6.4 Character/Font Drawing and BLT Attributes ......................................................................74 6.7 Display List ...................................................................................................................75 6.7.1 Overview ............................................................................................................................75 6.7.2 Header Format...................................................................................................................76 6.7.3 Display List Command Overview.......................................................................................77 6.7.4 Details of Display List Commands .....................................................................................81 7 Registers...............................................................................................................................93 7.1 Description....................................................................................................................93 7.1.1 Host Interface Registers ....................................................................................................94 7.1.2 Graphics Memory Interface Registers ...............................................................................98 7.1.3 Display Control Register ..................................................................................................101 7.1.4 Draw Control Registers....................................................................................................124 7.1.5 Draw mode Parameter Registers ....................................................................................127 7.1.6 Triangle Draw Registers ..................................................................................................141 7.1.7 Line Draw Registers ........................................................................................................144 7.1.8 Pixel Plot Registers..........................................................................................................145 7.1.9 Rectangle Draw Registers ...............................................................................................146 7.1.10 Blt Registers...................................................................................................................147 7.1.11 Fast2DLine Draw Registers ...........................................................................................148 7.1.12 Fast2DTriangle Draw Registers.....................................................................................149 7.1.12 DisplayList FIFO Registers ............................................................................................149 8 Timing Diagram ..................................................................................................................150 8.1 Host Interface .............................................................................................................150 8.1.1 CPU Read/Write Timing Diagram for SH3 Mode ........................................................................150 8.1.2 CPU Read/Write Timing Diagram for SH4 Mode ........................................................................151 8.1.3 CPU Read/Write Timing Diagram in V832 Mode ........................................................................152 8.1.4 SH4 Single-address DMA Write (Transfer of 1 Long Word)........................................................153 8.1.5 SH4 Single-address DMA Write (Transfer of 8 Long Words)......................................................154 8.1.6 SH3/4 Dual-address DMA (Transfer of 1 Long Word).................................................................155 8.1.7 SH3/4 Dual-Address DMA (Transfer of 8 Long Words) ..............................................................156 8.1.8 V832 DMA Transfer .........................................................................................................157 SH4 Single-address DMA Transfer End Timing ........................................................................158 8.1.10 SH3/4 Dual-address DMA Transfer End Timing............................................................159 8.1.11 V832 DMA Transfer End Timing ....................................................................................160 8.2 Graphics Memory Interface ........................................................................................161 8.2.1 Timing of Read Access to Same Row Address ...............................................................161 8.2.2 Timing of Read Access to Different Row Addresses .......................................................162 8.2.3 Timing of Write Access to Same Row Address ...............................................................163 8.2.4 Timing of Write Access to Different Row Addresses .......................................................164
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8.2.5 Timing of Read/Write Access to Same Row Address......................................................165 8.2.6 Delay between ACTV Commands ...................................................................................166 8.2.7 Delay between Refresh Command and Next ACTV Command......................................167 8.3 Display Timing ............................................................................................................168 8.3.1 Non-interlaced Video Mode .............................................................................................168 8.3.2 Interlaced Video Mode .....................................................................................................169 8.4 CPU Cautions .............................................................................................................170 8.5 SH3 Mode...................................................................................................................170 8.6 SH4 Mode...................................................................................................................171 8.7 V832 Mode .................................................................................................................171 8.8 DMA Transfer Modes Supported by SH3, SH4, and V832 ........................................171 9 Electrical Characteristics (Preliminary Target Specifications) ............................................172 9.1 Absolute Maximum Ratings........................................................................................172 9.2 Recommended Operating Conditions ........................................................................173 9.2.1 Recommended Operating Conditions .............................................................................173 9.2.2 Power-on Precautions .....................................................................................................173 9.3 DC Characteristics......................................................................................................174 9.4 AC Characteristics ..........................................................................................................175 9.4.1 Host Interface..........................................................................................................................175 9.4.2 Video Interface ........................................................................................................................176 9.4.3 Graphics Memory Interface.....................................................................................................177 9.4.4 PLL Specifications...................................................................................................................177 9.5 Timing Diagram ..........................................................................................................178 9.5.1 Host Interface...................................................................................................................178 9.5.2 Video Interface.................................................................................................................181 9.5.3 Graphics Memory Interface .............................................................................................183
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1 Overview
1.1 Introduction
Recent consumer information processing systems, such as car navigation systems, require graphics capabilities for web page browsing and 3D object manipulation. The required performance level for these graphics operations is also increasing. This MB86290A graphics controller provides an optimized solution for these new requirements. Target applications Car navigation systems Consumer information processing systems including digital STB Mobile IP terminals (Windows CE HPC/PPC) Consumer or arcade game machines
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1.2 System Configuration
The following figure shows an example of a car navigation system using MB86290A.
DRAM GPS Unit Main CPU
Flash
SDRAM Cache
Gyro sensor unit
IRC VICS Unit
DMAC
UART
Timer
MB86290A Graphics Controller
RGB
Monitor (LCD/CRT)
DVD Drive unit
DVD Decoder
Audio codec MIC PC Card PCMCIA I/F System bus
ADPCM
Speaker
Video I/F
Video
System Configuration
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1.3 Outline
High performance The maximum operating frequency is 100 MHz. At this speed, the pixel fill rate is 100 MPixels/sec (2D drawing without special effects).
Flexible display controller Display resolutions up to XGA (1024 x 768) and on-chip DAC are supported. The full screen can be split into two separate parts (left/right) each displaying different contents simultaneously. Smooth double-buffer-mode animation is supported. Each part of the screen can be scrolled independently. In addition, up to three screen layers can be overlaid. Alpha blending for transparent display of lower-layer contents is also supported. This function can be used to blend a navigation map onto a text window.
2D Rendering Anti-aliasing and alpha blending are supported to display high-quality graphics on low-resolution monitors.
3D Rendering Professional 3D rendering features, including perspective texture mapping, Gouraud shading, etc., are supported.
Others CMOS 0.25-m technology HQFP240 Package (lead pitch 0.5 mm) Supply voltage 2.5 V (internal)/3.3 V (I/O)
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1.4 Block Diagram
The MB86290A block diagram is shown below:
Host Interface
Host-bus
Draw Engine Display Control
Pre-processor PLL DDA Cursor Z Color Texture Color LUT Pattern FIFO Blender FIFO Blender D/ A Sync
Pixel-bus
Memory Control
MB86290A Block Diagram
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1.5 Functional Overview
1.5.1 System Configuration
Host CPU interface
MB86290A can be connected to Hitachi's SH3 or SH4 CPUs and NEC's V832 CPU without any glue logic. The host MB86290A CPU interface can drive the host CPU DMAC and transfer all graphical source data (display list, texture patterns, etc.) from the host (main) memory to it's internal registers (or external frame memory).
Graphics memory
Synchronous DRAM is attached externally. Either the 32-bit or 64-bit mode is supported as the interface with these external SDRAM devices. The external SDRAM operation frequency is the same as MB86290A (up to 100 MHz). Applicable memory device configurations are as follows: Graphics Memory Device Configuration
Type SDRAM 64 Mbit (x32 bit) SDRAM 64 Mbit (x32 bit) SDRAM 64 Mbit (x16Bit) Display signals
Data bus width 32 bit 64 bit 64 bit
# of devices 1 2 4
Total capacity 8 MB 16 MB 32 MB
MB86290A has three channels of 8-bit D/A converters and outputs analog RGB signals. Superimposing is possible by applying an external sync signal.
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1.5.2 Display Controller
Screen resolution
Various resolutions are achieved by using a programmable timing generator as follows: Screen Resolutions
Resolution 1024 x 768 1024 x 600 800 x 600 854 x 480 640 x 480 480 x 234 400 x 234 320 x 234 Display colors
There are two pixel color modes (indirect and direct). In the indirect mode, each pixel is expressed in 8-bit code. The actual display color is referenced using a color look-up table (color pallet). In this mode, each color of the lookup table is represented as 17 bits (RGB 6 bits each and independent alphablend bit), and 256 colors are selected from 262,144 colors. In the direct mode, each pixel is expressed as 16-bit code (RGB 5 bits each and reserved intensity bit). In this mode, 32,768 colors can be displayed.
TV/Video display
MB86290A can output a graphics image synchronized with external TV/video display signals. The graphics image can be overlapped at any area on the TV/video display window. MB86290A outputs a control signal to switch the display window externally. This scheme supports both interlace and non-interlace.
Overlay
Up to three extra layers can be overlaid on the base window. When multiple layers are overlaid, the lower layer image can be displayed according to the setting of the transparency option. Any codes in the color pallet can be assigned a transparent color. Code 0 in the indirect mode or color value 0 in the direct mode sets this transparent option.
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Hardware cursor
MB86290A supports two separate hardware cursor functions. Each of these hardware cursors is specified as a 64 x 64-pixel area. Each pixel of these hardware cursors is 8 bits and uses the indirect mode look-up table.
1.5.3 Frame Control
Double buffer scheme
This mode provides smooth animation. The display frame and drawing frame are switched back and forth at each scan frame. A program in the vertical blanking period controls flipping.
Scroll scheme
Wrap around scrolling can be done by setting the drawing area, display area, display size and start address independently.
Windows display
The whole screen can be split into two vertically separate windows. Both windows can be controlled independently.
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1.5.4 2D Drawing
2D Primitives
MB86290A provides automatic drawing of various primitives and patterns (drawing surfaces) to frame memory in either indirect color (8 bits/pixel referencing appropriate palette) or direct color (16 bits/pixel) mode. Alpha blending and anti-aliasing features are useful when the direct color mode is selected. A triangle is drawn in a single color, mapped with a style image formed by a single color or 2D pattern (tiling), or mapped with a texture pattern by designating coordinates of the 2D pattern at each vertex (texture mapping). Alpha blending can be applied either per entire shape in single color mode or per pixel in tiling/texture mapping mode. When an object is drawn in single color or filled with a 2D pattern (without using Gouraud shading or texture mapping), dedicated primitives, such as Fast2DLine and Fast2DTriangle, are used. Only vertex coordinates are set for these primitives. Fast2Dtriangle is also used to draw polygons. 2D Primitives Primitive type Point Line Triangle Fast2DLine Description Plots point Draws line Draws triangle Draws lines The number of parameters set for this primitive is less than that for Line. The CPU load to use this primitive is lighter than using Line. Draws triangles. When a triangle is drawn in one color or filled with a 2D pattern, the CPU load to apply this primitive is lighter than using Triangle.
Fast2DTriangle
Polygon draw
This function draws various random shapes formed using multiple vertices. There is no restriction on the number of vertices number, however, if any sides forming the random shape cross each other, the shape is unsupported. The Polygon draw flag buffer must be defined in graphics memory as a work field to draw random shapes.
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BLT/Rectangle fill
This function draws a rectangle using logical calculations. It is used to clear the frame memory and Z buffer. At scrolling, the rolled over part can be cleared by using this function in the blanking time period. BLT Attributes Attribute Raster operation Description Selects two source logical operation mode
Pattern (Text) drawing
This function draws a binary pattern (text) in a designated color. Pattern (Text) Drawing Attributes Attribute Enlarge Shrink Description 2x2 Horizontally x 2 Horizontally 1/2 1/2 x 1/2
Clipping
This function sets a rectangular window in a frame memory drawing surface and disables drawing of anything outside that window.
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1.5.5 3D Drawing
3D Primitives
This function draws 3D objects in frame memory in the direct color mode. 3D Primitives Primitive Point Line Triangle Description Plots 3D point Draws 3D line Draws 3D triangle
3D Drawing attributes
MB86290Ahas various professional 3D graphics features, including Gouraud shading and texture mapping with bi-linear filtering/automatic perspective correction, and provides high- quality realistic 3D drawing. A built-in sophisticated texture mapping unit delivers fast pixel calculations. This unit also delivers color blending between the shading color and texture color as well as alpha blending per pixel.
Hidden surface management
MB86290A supports the Z buffer for hidden surface management.
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1.5.6 Special Effects
Anti-aliasing
Anti-aliasing manipulates lines and borders of polygons in sub-pixel units to eliminate jaggies on bias lines. It is used as a functional option for 2D drawing (in direct color mode only).
Line drawing
This function draws lines of a specific width. Detecting a line pattern can also draw a broken line. The anti-aliasing feature is also useful to draw smooth lines. Line Draw Attributes Attribute Width Broken line Description Selectable from 1 to 32 pixels Set by 32 bit of broken line pattern
Alpha blending
Alpha blending blends two separate colors to provide a transparency effect. MB86290A supports two types of alpha blending; blending two different colors at drawing, and blending overlay planes at display. Transparent color is not used for these blending options. Alpha Blending Type Drawing Description - Transparent ratio set in particular register - While one primitive (polygon, pattern, etc.), being drawn, registered transparent ratio applied - Blends top layer pixel color and lower layer pixel at same position - Transparent ratio set in particular register - Registered transparent ratio applied during one frame scan
Overlay display
Shading
Gouraud shading is supported in the direct color mode to provide realistic 3D objects and color gradation.
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Texture mapping
MB86290A supports texture mapping to map a style pattern onto the surface of 3D polygons. Perspective correction is calculated automatically. For 2D pattern texture mapping, MB86290A has a built-in buffer memory for a field of up to 64 x 64 pixels. Texture mapping is performed at high speeds while texture patterns are stored in this buffer. The texture pattern can also be stored in the graphics memory. In this case, a large pattern of up to 256 x 256 pixels can be used. Texture Mapping Function Texture filtering Texture coordinate correction Texture blending Description - Bi-linear filter - Perspective - Stencil - Stencil alpha - Cramp Point sample Linear Decal Modulate Normal Stencil Repeat
Texture alpha blending
Texture wrap
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1.5.7 Display List
MB86290A is operated by feeding display lists which consists of a set of display commands, arguments and pattern data for them. Normally, these display lists are stored either in off- screen frame memory (part of MB86290A's local buffer) or host (main) memory that the DMAC of the host CPU can access directly. MB86290A reads these display lists, decodes the commands, and executes them after reading all the necessary arguments. By executing this operation set until the end of the display list, all graphics operations, including image/object drawing and display control, are separated from the CPU. Of course, the CPU program can also feed the display list information directly to MB86290A's designated registers.
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2 Signal Pins
2.1 Signals
2.1.1 Signals
D0-31 A2-24 BCLKI XRESET XCS XRD Host CPU Interface XWE0-3 XRDY XBS DREQ DRACK DTACK XINT MODE0-1 TEST0-5 HQFP240
MD0-63 MA0-13 MCKE MRAS MCAS MWE MDQM0-7 MCLKO Graphics Memory Interface
MB86290A Graphics Controller
MCLKI
DCLKO DCKLI AOUTR,G,B HSYNC VSYNC CSYNC Video Interface
CLK Clock input S CKM
EO GV VREF ACOMPR,G,B VRO
MB86290A Signals
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XINT DREQ XRDY D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VDDH VSS VDDL D10 D11 D12 D13 D14 D15 D16 VSS D17 D18 D19 D20 D21 D22 VDDH VSS VDDL D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS MD0 MD1 MD2 MD3 VDDH VSS VDDL MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13
2.2 Pin Assignment
2.2.1 Pin Assignment Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
MB86290A Pin Assignment
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MD14 61 MD15 62 MD16 63 MD17 64 VDDH 65 VSS 66 VDDL 67 MD18 68 MD19 69 MD20 70 MD21 71 MD22 72 MD23 73 MD24 74 VSS 75 MD25 76 MD26 77 MD27 78 MD28 79 MD29 80 MD30 81 MD31 82 VDDH 83 VSS 84 VDDL 85 DQM0 86 DQM1 87 DQM2 88 DQM3 89 MRAS 90 MCAS 91 MWE 92 MA0 93 MA1 94 MA2 95 MA3 96 MA4 97 VDDH 98 VSS 99 MA5 100 MA6 101 MA7 102 MA8 103 MA9 104 MA10 105 MA11 106 MA12 107 MA13 108 CKE 109 MCLKO 110 VDDH 111 VSS 112 VDDL 113 MCLKI 114 TEST5 115 VSS 116 DQM4 117 DQM5 118 DQM6 119 DQM7 120 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 TEST4 MODE1 MODE0 DCLKI VDDL VSS VDDH DCLKO HSYNC VSYNC CSYNC GV EO AVS4 AOUTR AVD4 VRO VREF ACOMPR AVS3 AVD3 AVS2 AOUTG AVD2 ACOMPG ACOMPB AVD1 AOUTB AVS1 TEST3 CKM A24 VSS A23 A22 A21 A20 A19 A18 VDDL VSS A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 VDDL VSS A7 A6 A5 A4 A3 A2
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 XWE3 XWE2 XWE1 XWE0 DTACK DRACK XRD XCS VDDL VSS BCLKI XBS TEST2 TEST1 TEST0 AVS0 S CLK AVD0(VCO) XRESET VDDL VSS MD63 MD62 MD61 MD60 MD59 MD58 MD57 VSS VDDH MD56 MD55 MD54 MD53 MD52 MD51 MD50 VSS MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 VDDL VSS VDDH MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32
2.2.2 Pin Assignment Table
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name XINT DREQ XRDY D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VDDH VSS VDDL D10 D11 D12 D13 D14 D15 D16 VSS D17 D18 D19 D20 D21 D22 VDDH VSS VDDL D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS MD0 MD1 MD2 MD3 VDDH VSS VDDL MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name MD14 MD15 MD16 MD17 VDDH VSS VDDL MD18 MD19 MD20 MD21 MD22 MD23 MD24 VSS MD25 MD26 MD27 MD28 MD29 MD30 MD31 VDDH VSS VDDL DQM0 DQM1 DQM2 DQM3 MRAS MCAS MWE MA0 MA1 MA2 MA3 MA4 VDDH VSS MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 CKE MCLKO VDDH VSS VDDL MCLKI TEST5 VSS DQM4 DQM5 DQM6 DQM7 No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin Name MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 VDDH VSS VDDL MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 VSS MD50 MD51 MD52 MD53 MD54 MD55 MD56 VDDH VSS MD57 MD58 MD59 MD60 MD61 MD62 MD63 VSS VDDL XRESET AVD0(VCO) CLK S AVS0 TEST0 TEST1 TEST2 XBS BCLKI VSS VDDL XCS XRD DRACK DTACK XWE0 XWE1 XWE2 XWE3 No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin Name A2 A3 A4 A5 A6 A7 VSS VDDL A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VSS VDDL A18 A19 A20 A21 A22 A23 VSS A24 CKM TEST3 ACOMPB AVD1 AOUTB AVS1 ACOMPG AVD2 AOUTG AVS2 AVD3 AVS3 AVS4 AOUTR AVD4 VRO VREF ACOMPR EO GV CSYNC VSYNC HSYNC DCLKO VDDH VSS VDDL DCLKI MODE0 MODE1 TEST4
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VSS/AVS: Ground AVD: 2.5-V Analog power supply
VDDH: 3.3-V power supply
VDDL: 2.5-V power supply
AVD(VCO): 2.5-V PLL power supply
Note 1: Do not connect anything to pin 211 Note 2: These power supply layers (AVD/AVD(VCO)/VDDL) are recommended to physically isolate each other on the PCB.
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2.3 Signal Descriptions
2.3.1 Host CPU Interface
Host CPU Interface Signals Signal Name MODE0-1 XRESET D0-31 A2-A24 BCLKI XBS XCS XRD XWE0 XWE1 XWE2 XWE3 XRDY I/O Input Input In/Out Input Input Input Input Input Input Input Input Input Output Tri-state Description Host CPU Mode selection Hardware reset Host CPU bus data Host CPU bus address (In the V832 mode, A[24] is connected to XMWR.) Host CPU bus clock Bus cycle start Chip select Read strobe Write strobe for D0-D7 Write strobe for D8-D15 Write strobe for D16-D23 Write strobe for D24-D31 Wait request signal (In the SH3 mode, when this signal is 0, it indicates the wait state; in the SH4 and V832 modes, when this signal is 1, it indicates the wait state.) DMA request signal (This signal is low-active in both the SH mode and V832 mode.) Acknowledge signal issued in response to DMA request (DMAAK is used in the V832 mode; this signal is high-active in both the SH mode and V832 mode.) DMA transfer strobe signal (XTC is used in the V832 mode. In the SH mode, this signal is high-active; in the V832 mode, it is low-active.) Interrupt signal issued to host CPU (In the SH mode, this signal is low-active; in the V832 mode, it is highactive) Test signals
DREQ DRACK/DMAAK
Output Input
DTACK/XTC
Input
XINT
Output
TEST0-5
Input
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MB86290A can be connected to the Hitachi SH4 (SH7750), SH3 (SH7709/09A) and NEC V832. In the SRAM interface mode, MB86290A can be used with any other CPU as well. The host CPU is specified by the MODE pins. MODE 1 L L H H MODE 2 L H L H CPU SH3 SH4 V832 Reserved
The host interface data bus is 32-bits wide (fixed). The address bus is 24-bits wide (per double word), and has a 32Mbyte address field. MB86290A uses a 32-Mbyte address field. The external bus frequency is up to 100 MHz. In the SH4 mode and V832 mode, when the XRDY signal is low, it is in the ready state. In the SH3 mode, when the XRDY signal is low, it is in the wait state. DMA data transfer is supported using an external DMAC. An interrupt request signal is generated to the host CPU. The XRESET input must be kept low (active) for at least 300 s after setting the S (PLL reset) signal to high. TEST signals must be clamped to high level. In the V832 mode, MB86290A signals are connected to the V832 CPU as follows: MB86290A Signal Pins A24 DTACK DRACK V832 Signal Pins XMWR XTC DMAAK

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2.3.2 Video Interface
Video Interface Signals Signal Name DCLKO DCLKI AOUTR AOUTG AOUTB HSYNC I/O Output Input Analog output Analog output Analog output I/O*1 Description Dot clock signal for display Dot clock input for external synchronization Analog signal (R) output Analog signal (G) output Analog signal (B) output Horizontal sync signal output Horizontal sync input in external sync mode Vertical sync signal output Vertical sync input in external sync mode Composite sync signal output Even/odd field identification output , this signal is input for even/odd field identification input. GV VREF ACOMPR ACOMPG ACOMPB VRO Output Analog input Analog output Analog output Analog output Analog output Graphics/Video switch Reference voltage input R Signal complement output G Signal complement output B Signal complement output Reference current output
VSYNC
I/O*1
CSYNC EO
Output I/O*1
*1: Tolerates 5-V input voltage level
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Contains 8-bit precision D/A converters and outputs analog RGB signals Uses CSYNC signal and external circuits to generate composite video signal Can output analog RGB signals synchronously to external video signal Can synchronize to either DCLKI signal input or internal dot clock HSYNC and VSYNC reset to output mode. These signals must be pulled up externally. AOUTR, AOUTG and AOUTB must be terminated at 75 . 1.1 V is input to VREF. A bypass capacitor (with good highfrequency characteristics) must be inserted between VREF and AVS. ACOMPR, ACOMPG and ACOMPB are tied to analog VDD via 0.1-F ceramic capacitors. VRO must be pulled down to analog ground by a 2.7-k resistor. HSYNC, VSYNC and EO can tolerate input voltage levels of 5 V. However, NEVER input 5 V to these pins when power is not supplied to MB86290A. (See the maximum voltage specification in the electrical characteristics.) When producing a non-interlaced display in the external synchronous mode, input 0 to the EO pin by using a pull-down resistor, etc. The GV signal switches graphics and video at chroma key operation. When video I is selected, the L level is output.
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2.3.3 Graphics Memory Interface
Graphics Memory Interface Signals Signal Name MD0-63 MA0-13 CKE MRAS MCAS MWE MDQM0-7 MCLKO MCLKI I/O In/Out Output Output Output Output Output Output Output Input Description Graphics memory bus data Graphics memory bus address Clock enable Row address strobe Column address strobe Write enable
Data mask
Graphics memory clock output Graphics memory clock input
This interface is used to transfer data from/to external memory. 64Mbit SDRAM can be used without glue logic. The data bus width is set to either 64 or 32 bits. In the 32-bit mode, MD32-63 and MDQM4-7 must be kept open. MCLKI and MCLKO are tied to each other externally.
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2.3.4 Clock Input
Clock Input Signals Signal Name CLK S CKM I/O Input Input Input Description Clock input signal PLL reset signal Clock mode signal
Inputs source clock for generating internal operation clock and display dot clock. Normally, 4 Fsc(= 14.31818 MHz) is input. An internal PLL generates the internal operation clock of 100.22726 MHz and the display base clock of 200.45452 MHz. For the internal operation clock, use either the output clock of the internal PLL (x7 of input clock) or the bus clock input (BCLK1) from the host CPU. When the host CPU bus speed is 100 MHz, the BCLK1 input should be selected. CKM L H Clock mode Output from internal PLL selected Host CPU bus clock (BCLK1) selected
At power-on, a low-level signal must be input to the S-signal pin for more than 500 ns and then set to high. After the S-signal input is set to high, a low-level signal must be input to XRESET for another 300 s.
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3 Host Interface
3.1 Operation Mode
3.1.1 Host CPU Mode
Select the host CPU by setting the MODE signals as follows: CPU Type Setting MODE1 L L H H MODE0 L H L H CPU SH3 SH4 V832 Reserved
3.1.2 Endian
MB86290A operates in little-endian mode. All the register address descriptions in these specifications are byte address in little endian. When using a big-endian CPU, note that the byte or word addresses are different from these descriptions.
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3.2 Access Mode
3.2.1 SRAM Interface
Data can be transferred to/from MB86290A using a typical SRAM access protocol. MB86290A internal registers, internal memory and external memory are all mapped to the physical address field of the host CPU. The host CPU can access any of them like a normal memory device. Since MB86290A uses a hardware wait using the XRDY signal output, the respective hardware wait option of the host CPU must be enabled.
CPU Read
The host CPU reads data from internal registers and memory of MB86290A in double-word (32 bit) units.
CPU Write
The host CPU writes data to internal registers and memory of MB86290A in byte units.
3.2.2 FIFO Interface
This interface transfers display lists in host memory. Display list information is transferred efficiently by using a single address mode DMA operation. This FIFO is mapped to the physical address field of the host CPU so that the same data transfer can be performed in either the SRAM mode or dual address DMA mode by specifying the FIFO in the destination address.
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3.3 DMA Transfer
3.3.1 Data Transfer Unit
DMA transfer is performed in double-word (32 bit) units or 8 double-word (32 Byte) units. Byte and word access is not supported. Note: 8 double-word transfer is supported only in the SH4 mode.
3.3.2 Address Mode
Dual address mode DMA is performed at memory-to-memory transfer between host memory (source) and MB86290A internal registers, memory, or external memory (destination). Both the host memory address and destination address is used. In
the SH4 mode, the 1 double-word transfer (32 bits) and 8 double-word transfer (32 bytes) can be used. When the CPU transfer destination address is fixed, data can also be transferred to the FIFO interface. However, in this case, even the SH4 mode supports only the 1 double-word transfer. Note: The SH3 mode supports the direct address mode; it does not support the indirect address mode.
Single address mode (FIFO interface)
DMA is performed between host memory (source) and FIFO (destination). Address output from the host CPU is only applied to designate the source, and the data output from the host memory is transferred to the FIFO using the DACK signal. In this mode, data read from the host memory and data write to the FIFO occur in the same bus cycle. This mode does not support data write to the host memory. When the FIFO is full, the DREQ signal is tentatively negated and the DMA transfer is suspended until the FIFO has room for more data. The 1 double-word transfer (32 bits) and the 8 double-word transfer (32 Bytes) can be used. Note: The single-address mode is supported only in the SH4 mode.
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3.3.3 Bus Mode
MB86290A supports the DMA transfer cycle steal mode and burst mode. Either mode is selected by setting to the external DMA mode.
Cycle steal mode (In the V832 m o de, the burst m o de is called the single transfer
m o de.) In the cycle steal mode, the bus right is transferred back to the host CPU at every DMA transaction unit. The DMA transaction unit is either 1 doubleword (32 bits) or 8 double-words (32 B).
Burst mode (In the V832 m ode, the burst m o de is called the dem and transfer m o de.)
When DMA transfer is started, the right to use the bus is acquired and the transfer begins. The data transfer unit can be selected from between the 1 double word (32 bits) and 8 double words (32 B).
Note: When performing DMA transfer in the dual-address mode, a function for automatically negating DREQ is provided based on the setting of the DBM register.
3.3.4 DMA Transfer Request
Single-address mode DMA is started when the MB86290A issues an external request to DMAC of the host processor. Set the transfer count in the transfer count register of the MB86290A and then issue DREQ. Fix the CPU destination address to the FIFO address.
Dual-address mode DMA is started by two procedures: the MB86290A issues an external request to DMAC of the host processor, or the CPU itself is started (auto request mode, etc.). Set the transfer count in the transfer count register of MB86290A and then issue DREQ. Note: The V832 mode requires no setting of the transfer count register.
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3.3.5 Ending DMA Transfer
SH3/SH4 When the MB86290A transfer count register is set to 0, DMA transfer ends and DREQ is negated.
V832 When the XTC signal from the CPU is low-asserted while the DMAAK signal to MB86290A is high-asserted, the end of DMA transfer is recognized and DREQ is negated.
The end of DMA transfer is detected in two ways: the DMA status register (DST) is polled, and an interrupt to end the drawing command (FD000000h) is added to the display list and the interrupt is detected.
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3.4 Interrupt Request
MB86290A issues interrupt requests to the host CPU. The following events issue interrupt requests. An interrupt request caused by each of these events is enabled/disabled independently by IMR (Interrupt Mask Register).

External synchronization error Vertical synchronization timing detect Field synchronization timing detect Command error Command complete
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3.5 Transfer of Local Display List
This is the mode in which the MB86290A internal bus is used to transfer the display list stored in the graphics memory to the FIFO interface. During transfer of the local display list, the host bus can be used to perform read/write for the CPU. How to transfer list: Store the display list in the local memory of the MB86290A, set the transfer source local address (LSA) and the transfer count (LCO), and then issue a request (LREQ). Whether or not the local display list is currently being transferred is checked using the local transfer status register (LSTA).
CPU
FIFO
Host IF Memory IF
SDRAM
SDRAM
CPU Bus
Internal Bus
Fig. 3.1 Transfer Path for Local Display List
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3.6 Memory Map
The following table shows the memory map of MB86290A to the host CPU address field. The physical address is mapped differently in each CPU type (SH3, SH4 or V832).
64 MB Field (SH3/SH4) 16 MB Field (V832)
32 MB-256 KB
Graphics memory field
0000000-1FBFFFF
16 MB-256 KB
Graphics memory field
0000000-0FBFFFF
256 KB
Register field
1FC0000-1FFFFFF
256 KB
Register field
0FCFFFF-0FFFFFF
32 MB
Reserved
2000000-3FFFFFF
Fig. 3.2 Memory Map
Table 3-1 Address Mapping in SH3/SH4 Mode Size 32 MB to 256 KB 64 KB 64 KB 64 KB 64 KB 32 KB Resource Graphics memory Host interface registers Display engine registers Internal texture memory Drawing engine registers Reserved * Base address 00000000 01FC0000 01FD0000 01FE0000 01FF0000 02000000 (HostBase) (DisplayBase) (TextureBase) (DrawBase) (Name)
The memory contents of 00000000-01FFFFFF are duplicated in this reserved field.
Table 3-2 Address Mapping in V832 Mode Size 32 MB to 256KB 64 KB 64 KB 64 KB 64 KB Resource Graphics memory Host interface registers Display engine registers Internal texture memory Drawing engine registers Base address 00000000 00FC0000 00FD0000 00FE0000 00FF0000 (HostBase) (DisplayBase) (TextureBase) (DrawBase) (Name)
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4 Graphics Memory
4.1 Configuration
MB86290A uses local external memory (Graphics Memory) for drawing and display management. The configuration of this Graphics Memory is described as follows:
4.1.1 Data Type
MB86290A handles the following types of data. Display list can be stored in the host (main) memory as well. Texture-tiling pattern and text pattern can be defined by a display list as well.
Drawing frame
This is a rectangular image data field for 2D/3D drawing. Two or more drawing frames can be used at once. The frame size can be bigger than the display frame size and display part of it. The drawing frame can be applied in 32-pixel units (both horizontally and vertically), and the maximum size is 4096 x 4096. Both direct and indirect color modes can be used.
Display frame
This is a rectangular image data field for display. Up to four layers (three of graphics and one of video/graphics) can be overlaid and displayed at once. From bottom to the top, these are called the B (Base), M (Middle), W (Window), and C (Console) layers.
Z buffer
The Z buffer eliminates hidden surfaces in 3D drawing. The configuration is the same as drawing frame (defined for 3D drawing). 2 bytes/pixel of memory resources must be assigned. The Z buffer must be cleared prior to 3D drawing.
Polygon draw flag buffer
This is a work field for random shape drawing of multiple vertices. 1 bit/pixel should be defined for the drawing shape. This flag buffer must be cleared prior to drawing.
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Display list
This is a set of commands and parameters executed by MB86290A.
Texture pattern
This is pattern data for texture mapping. The 16-bit direct color mode must be used for texture pattern. The maximum size of this pattern is 256 x 256 pixels. The texture pattern is referenced from either graphics memory or internal texture buffer.
Cursor pattern
This is the pattern data for hardware cursors. Each pixel is described in 8-bit indirect color mode. Two sets of 64 x 64-pixel patterns can be used.
4.1.2 Memory Layout
Each of these data items can be allocated anywhere in the Graphics Memory according to the respective register setting.
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4.1.3 Memory Data Format
Direct color
Color data is described in 15-bit RGB (RGB 5 bits, respectively). Bit 15 is used as the alpha bit when producing a semi-transparent display for the Clayer. For other layers, set bit 15 to 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A
R
G
B
Indirect color
The color index code is in 8 bits.
7
6
5
4
3
2
1
0
Color Code
Z value
This unsigned integer data describes the Zvalue in a 3D coordinate.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unsigned Integer
Polygon draw flag
This is binary data describing each pixel in 1 bit.
15 P15
14 P14
13 P13
12 P12
11 P11
10 P10
9 P9
8 P8
7 P7
6 P6
5 P5
4 P4
3 P3
2 P2
1 P1
0 P0
31 P31
30 P30
29 P29
28 P28
27 P27
26 P26
25 P25
24 P24
23 P23
22 P22
21 P21
20 P20
19 P19
18 P18
17 P17
16 P16
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Texture/tiling pattern (direct color)
This is color data described in the direct color mode (RGB 5 bits, respectively). The MSB is an alpha bit used for the transparency effect of alpha blending.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A
R
G
B
Tiling pattern (indirect color)
This is a color index code in 8 bits.
7
6
5
4
3
2
1
0
Color Code
Cursor pattern
This is a color index code in 8 bits.
7
6
5
4
3
2
1
0
Color Code
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4.2 Frame Management
4.2.1 Single Buffer
The entire or partial area of the drawing frame is assigned as a display frame. The display field is scrolled by relocating the position of the display frame. When the display frame crosses the border of the drawing frame, the other side of the drawing frame is displayed, assuming that the drawing frame is rolled over (top and left edges assumed logically connected to bottom and right edges, respectively). To avoid the affect of drawing on display, the drawing data can be transferred to the Graphics Memory in the blanking time period.
4.2.2 Double Buffer
Two drawing frames are set. While one frame is displayed, drawing is done at the other frame. Flicker-less animation can be performed by flipping these two frames back and forth. Flipping is done in the blanking time period. There are two flipping modes: automatically at every scan frame period, and by user control. The double buffer is assigned independently for the Base and Middle layers. When the screen partition mode is selected (so that both Base and Middle layers split into separate left and right windows), the double buffer can be assigned independently for left and right windows.
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4.3 Memory Access
4.3.1 Memory Access by Host CPU
The Graphics Memory is mapped to the host CPU physical address field. The host CPU can access the Graphics Memory of MB86290A like a typical memory device.
4.3.2 Priority of Memory Access
The Graphics Memory accesses priority is as follows: 1. Refresh 2. Display 3. Host CPU Access 4. Drawing
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5 Display Controller
5.1 Overview
Display control
Overlay of four display layers, screen partition, scroll, etc., is applicable.
Video timing generator
The video display timing is generated according to the display resolution (from 320 x 240 to 1024 x 768).
Color look-up
There are two sets of color look-up tables (pallet RAM) for the indirect color mode (8 bits/pixel).
Cursor
Two sets of hardware cursor patterns (8 bits/pixel, 64 x 64 pixels each) can be used.
External synchronization control
Graphics display can be synchronized with the external video display timing.
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5.2 Display Function
5.2.1 Layer Configuration
MB86290A supports four layers of display frames (C, W, M and B). Furthermore, the M and B layers can be split into two separate windows at any position (L frame and R frame). All these six frames are assigned as logically separated fields in the Graphics Memory.
C-layer (Console layer) Top frame for console display 8, 16 bits/pixel
W-layer (Window layer) 16 bits/pixel
M-layer (Middle layer) Additional overlay data 8,16 bits/pixel split into two partitions B-layer (Base layer) Navigation map data 8,16 bits/pixel split into two partitions
Configuration of Display Layers
When the resolution exceeding the VGA (640 x 480) is required, the layer count or pixel data which can be simultaneously displayed is restricted according to the capability of frame memory for supplying data.
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5.2.2 Overlay
Simple priority mode
The top layer has the higher priority. Each pixel color is determined according to the following rules: 1. If the C layer is not transparent, the C-layer color is displayed. 2. If the C layer is transparent and W-layer image is at that position, the W-layer color is displayed. 3. If the C layer is transparent and there is no W layer image at that position, and if the M-layer color is not transparent, the M-layer color is displayed. 4. If the C and M layers are transparent and there is no W-layer image at that position, the B-layer color is displayed. Transparent color is set by putting a specific transparent color code in the register.
Blend mode
The W, M and B layers are managed in the same way as the simple priority mode described above. The result of the W/M/B layer priority color is blended with the C-layer color according to the blending ratio specified in the register. This mode is applied when the alpha bit of that pixel in the C layer is 1. If this alpha bit is set to 0, the result is the same as the simple priority mode. When the C-layer display priority is cursor display, the cursor color and C layer color are alpha blended at the pixel position with alpha bit = 1. The alpha blend ratio is calculated as follows:
When BRS bit of BRATIO register = 0 Display color = ((C layer color x blend coefficient) + (Mixed color of W/M/B layers x (1-blend coefficient)) When BRS bit of BRATIO register = 1 Display color = (C layer color x (1-blend coefficient)) + (Mixed color of W/M/B layers x blend coefficient)
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5.2.3 Display Parameters
The display field is specified according to the following parameters. Each parameter is set independently at the respective register.
HTP HSP HDP HDB WY HSW
VDP
WX
VSP
WW WH
VTR VSW
Display Parameters
HTP HSP HSW HDP HDB VTR VSP VSW VDP WX WY WW WH Horizontal Total Pixels Horizontal Synchronize pulse Position Horizontal Synchronize pulse Width Horizontal Display Period Horizontal Display Boundary Vertical Total Raster Vertical Synchronize pulse Position Vertical Synchronize pulse Width Vertical Display Period Window position X Window position Y Window Width Window Height
When not splitting the screen, set HDP to HDB and display only the left side of the screen. The settings must meet the following size relationship: 0 < HDB HDP < HSP < HSP + HSW + 1 < HTP 0 < VDP < VSP < VSP VSW + 1 < VTR HDP - HDB > 4 (in direct color mode), 8 (in indirect color mode)
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5.2.4 Display Position Control
The graphic image data to be displayed is located in the logical 2D coordinate area (logical graphics field) in the Graphics Memory. There are six logical graphics fields as follows: C layer W layer ML layer (left field of M layer) MR layer (right field of M layer) BL layer (left field of B layer) BR layer (right field of B layer) The correlation between the logical graphics field and physical display position is defined as follows:
Origin Address (OA) Stride (W) Logical Frame Display Address (DA) Display Position X,Y (DX,DY)
Height (H)
Display Frame VDP
HDP
Display Position Parameters
OA W H DA DX DY
Origin Address Stride Height Display Address Display Position
Base address of logical graphics field. Memory address of top left edge pixel in logical graphics field Width of logical graphics field. Defined in 64-byte boundary Height of logical graphics field. Total raster (pixel) count of field Display base address. Top left position address of display frame Display base 2D coordinate
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MB86290A scans the logical graphics field as if the entire field is rolled over in both the horizontal and vertical directions. By using this function, if the display frame crosses the border of the logical graphics field, the part outside the border is covered with the other side of the logical graphics field, which is assumed to be connected cyclically as shown below:
Logical Frame Origin W
Additionally drawn parts L
Previous origin
display
New display origin
Wrap Around Management of Display Frame
The relational expression of the X- and Y-coordinates in the frame and their corresponding linear addresses (in bytes) is shown below. A(x,y) = x x bpp/8 + 64wy (bpp = 8 or 16)
The origin of the displayed coordinates must be within the frame. To be more specific, the parameters are subject to the following constraints: 0 DX < w i 64 x 8/bpp (bpp = 8 or 16) 0 DY < H
DX, DY, and DA must indicate the same point within the frame. In other words, the following relationship must be established. DA = OA + DX x bpp/8 + 64w i DY (bpp = 8 or 16)
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5.3 Display Color
Either direct color mode (16 bits/pixel) or indirect color mode (8 bits/pixel) can be used for the C, M, and B layers. Only the direct color mode can be used for the W layer.
5.3.1 Color Look-up Table
MB86290A has two color look-up tables (pallets) for the indirect color mode. Each pallet has 256 entries. A color data item contains 18 bits of data (RGB 6 bit, respectively), which is correlated to each color code specified in 8-bit data. Therefore, each pallet can show 256 colors at one time out of 262,144 color selections.
C-layer palette
This pallet is dedicated to the C layer and hardware cursors. If the overlay blend mode is used, an alpha bit must be set at each color data. When this alpha bit is set to 1, color blending between the C-layer pixel and W/M/B layer pixels is performed according to the priority order specified in the overlay section. This blending option cannot be used for the hardware cursor.
M/B-layer palette
This pallet is shared by the M and B layers. If both the M and B layers are set to the indirect color mode, they share this same color pallet.
5.3.2 Chroma-key Operation
MB86290A performs superimpose using the chroma-key function. When the key color of this chroma-key operation matches the color of the C layer during the display scan period, the GV signal output becomes L level. The graphics signal output from MB86290A and the external video signal can be switched by using this signal.
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5.4 Cursor
5.4.1 Cursor Display Function
MB86290A can display two hardware cursors simultaneously. Each cursor is specified as 64 x 64 pixels, and the style pattern is set in the Graphics Memory. Only the indirect color mode (8 bits/pixel) can be used and the Clayer pallet is used for the color look-up. However, transparent color management (transparent color code setting and management of code 0) is different from ordinary C-layer pixelsalpha blending cannot be used for the cursor color and the alpha bit in the color data registered to the color palette is ignored.
5.4.2 Cursor Management
The display priority for hardware cursors is programmable. The cursor can be displayed either on top or underneath the C layer using this feature. A separate setting can be made for each hardware cursor. If part of a hardware cursor crosses the display frame border, the part outside the border is not shown. However, with cursor 1 displayed over the C-layer and cursor 0 displayed under the C-layer, the cursor 1 display has priority over the cursor 0 display.
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5.5 Processing Flow for Display Data
Processing such as layer overlapping (superimposing) and chroma key is performed as follows:
M-layer B-layer W-layer ML-layer Transparent Color Overlap by Color Priority MR-layer Transparent Color Color Pallet for M&B
Cursor0 Cursor1 C-layer
Overlap by Priority
Pallet for C
C-layer Transparent Color Cursor Overlap Mode Color Cursor Transparent Color Color
bitpixel
Select
Select
bitpixel
Overlap by Priority
Blend
Blend Mode Blend Ratio
Blend Enable
Select C-layer Chroma Key Mode
Select
DAC
Compare
Key Color
Analog RGB output
GV output
Fig. 5.1 Display data processing flow ML-layer Transparent Color Specifies transparent color code for left side of M layer The color code corresponding to the transparent color is used to output transparent image data for the lower layer. ML-layer Transparent Color Specifies transparent color code for right side of M layer The color code corresponding to the transparent color is used to output transparent image data for the lower layer.
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C-layer Transparent Color Specifies transparent color code for C layer The color code corresponding to the transparent color is used to output transparent image data for the lower layer. Cursor Transparent Color Specifies transparent color code for cursor Cursor Priority Mode Specifies whether or not to display cursor above C layer Blend Mode Defines correspondence between blend coefficients and variables used when applying blend coefficients Blend ratio Specifies blend ratio with accuracy of 1/16 Blend Enable Specifies whether or not to use Blend Chroma Key Mode Selects display data used to compare chroma keys The data for the C-layer or final tier can be selected. Key Color Sets color code compared with display data When display data matches the color code, 0 is output to the GV pin.
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5.6 Synchronization Control
5.6.1 Applicable Display Resolution
The following table shows typical display resolutions and their sync signal frequencies. The pixel clock frequency is determined by setting the division rate of the display reference clock. The display reference clock is either the internal PLL (200.45452 MHz at input frequency of 14.31818 MHz), or the clock supplied to the DCLKI input pin. The following table gives the clock division rate used when the internal PLL is the display reference clock:
Resolution 320 x 240 400 x 240 480 x 240 640 x 480 854 x 480 800 x 600 1024 x 768
Division rate of reference clock 1/30 1/24 1/20 1/8 1/6 1/5 1/3
Pixel frequency 6.7 MHz 8.4 MHz 10.0 MHz 25.1 MHz 33.4 MHz 40.1 MHz 66.8 MHz
Horizontal total pixel count 424 530 636 800 1062 1056 1389
Horizontal frequency 15.76 kHz 15.76 kHz 15.76 kHz 31.5 kHz 31.3 kHz 38.0 kHz 48.1 kHz
Vertical total raster count 263 263 263 525 525 633 806
Vertical frequency 59.9 Hz 59.9 Hz 59.9 Hz 59.7 Hz 59.9 Hz 60.0 Hz 59.9 Hz
Pixel frequency = 14.31818 MHz x 14 x reference clock division rate (when internal PLL selected) = DCLKI input frequency x reference clock division rate (when DCLKI selected) Horizontal frequency = Pixel frequency/Horizontal total pixel count Vertical frequency = Horizontal frequency/Vertical total raster count
5.6.2 Interlace Display
The MB86290A can generate both a non-interlace display and an interlace display. For the interlace display, the 1st, 3rd, ... (2n+1)th rasters of the display screen are output to odd fields, and 2nd, 4th, ... 2n-th rasters of the display screen are output to even fields.
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5.6.3 External Synchronization
Display scan can also be synchronized to external HSYNC/VSYNC signals. When the external synchronization mode is set at the register, MB86290A starts sampling the HSYNC signal input and displays the graphics output synchronized to the external video signals. Either the internal display base clock or DCLKI input can be used for this sampling clock. Also, by using the chroma-key function, superimpose is performed with external circuitry as follows:
External Sync Enable Hsync In Vsync In EO In 3 states buffer Hsync Out Vsync Out EO Out
ESY bit HSYNC
Display Timming Generator
VSYNC Analog RGB Out Overlap C
EO
Cursor 0 Cursor 1
CKM bit
MB86290A
KEYC register
Compare GV
Analog RGB In Video SW
(Pedestal Clump Input)
Superimposed Analog RGB Out
Fig. 5.2 Example of External Synchronization Circuit The external synchronous mode is set using the ESY bit of the DCM register. When the external synchronous mode is set, the HSYNC, VSYNC, and EO pins of the MB86290A are placed in the input mode. After this, supply external sync signals by using the tristate buffer. Also, when exiting from the external synchronous mode, cut the external synchronous input and then set the internal ESY bit of the MB86290A to OFF. With the MB86290A sync signal output set to ON, avoid setting the buffer for external sync signals to ON. Use the above procedure to control so that the concurrent-ON duration will not occur.
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DAC
C W M B
Horizontal synchronization is controlled by the following state transitions:
Otherwis Disp
Horizontal pixel counter reaches HTP
Horizontal pixel counter reaches HDP
Otherwis Fporch
Horizontal pixel counter reaches HSP
External horizontal synchronization detected, or horizontal synchronization pulse counter reaches HSW
Bporch Otherwis
When horizontal pixel counter reaches HTP, counter initialized
Sync Otherwis
Horizontal pixel counter suspended and horizontal synchronization pulse counter starts counting
State transitions are controlled mainly using the count values of the horizontal pixel counter. The display duration is equivalent to the Disp state. When the value of the horizontal pixel counter reaches the setting of the HDP register, the display duration ends, causing a transition from the Disp state to the Fporch state (front porch). With the Fporch state established, when the value of the horizontal pixel counter reaches the setting of the HSP register, a transition is made to the Sync state. In the Sync state, external horizontal synchronization signals are supplied. The MB86290A detects the negation edge of the external horizontal synchronization pulse to perform synchronization. When the external horizontal synchronization signal is detected, a transition is made to the Bporch state (back porch). In the Sync state, the horizontal pixel counter stops, but the horizontal synchronization pulse counter starts incrementing from 0. When the value of the counter reaches the setting of the HSW register, a transition is made to the Bporch state without detecting the external horizontal synchronization signal. With the Bporch state established, when the value of the horizontal pixel counter reaches the setting of the HTP register, the horizontal pixel counter is reset and a transition is made to the Disp state, starting display of the next raster.
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The vertical synchronization is controlled by the following state transitions:
Otherwis Disp
Raster counter reaches VDP
Otherwis Fporch
Assertion of external vertical synchronization pulse detected
Raster counter reaches VTR
Bporch Otherwis
Negation of external vertical synchronization pulse detected
Sync Otherwis
Counter initialized when raster counter reaches VTP
State transitions are mainly controlled using the count values of the raster counter. The display duration is equivalent to the Disp state. When the value of the raster counter reaches the setting of the VDP register, the display duration ends, causing a transition from the Disp state to the Fporch state (front porch). In the Fporch state, the processing waits for the external vertical synchronization pulse to be asserted. When assertion of the external vertical synchronization pulse is detected, a transition is made to the Sync state. In the Sync state, the processing waits for the external vertical synchronization signal to be negated. When the negation is detected, a transition is made to the Bporch state (back porch). With the Bporch state established, when the value of the raster counter reaches the setting of the VTR register, the raster counter is reset and a transition is made to the Disp state, starting display of the next field.
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5.7 Video Interface
5.7.1 NTSC Output
If an NTSC signal is required, an NTSC encoder device should be connected externally as shown below:
MB86290A AOUTR AOUTG AOUTB
MB3516A R-IN G-IN VIDEO-OUT B-IN
CSYNC
CSYNC-IN
Fig. 5.3 Example of NTSC Encoder Connection
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6 Drawing Control
6.1 Coordinates
6.1.1 Drawing Coordinate
MB86290A manages a drawing frame as a 2D coordinate with the origin at the top left edge. The maximum coordinate is 4096 x 4096. Each drawing frame is located in the Graphics Memory by setting the address of the origin and width (pixel size of X span). Although the maximum size of Y span does not need to be specified, take care about the memory size allocation so as not to overlap any other frames. Also, setting the clip field (top left and bottom right coordinates in registers) prevents drawing of all images outside the border of the clip window.
X (max. 4096* j Base Point Draw frame size X
(Xmin, Ymin) Draw frame size Y Clip border
Y (Max. 4096)
(Xmax, Ymax)
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6.1.2 Texture Coordinate
This is another 2D coordinate specified as S and T (S: horizontal, T: vertical). Any integer in a range of i512 to +511 can be used as the S and T coordinates. The texture coordinate is correlated to the 2D coordinate of a vertex. All vertices forming a polygon have correlated texture coordinates. One texture style pattern can be applied to up to 256 x 256 pixels. The applied texture size is set in the register. When the S and T coordinate exceeds the maximum size of the texture style pattern, the repeat, cramp or border color option is selected.
S(Max.+512/-512)
T(Max.+512/-512)
Max.256pixel
Texture pattern
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Max.256pixel
Base Point
6.1.3 Frame Buffer
For drawing, the following area must be assigned to the Graphics Memory. The frame size (number of pixels on X span) is common for these areas.
Drawing frame
The results of drawing are contained in the graphical image data area. Both the direct and indirect color mode are applicable.
Z buffer
nts area dr used to eliminate hidden surfaces in drawinga3D graphics. 2i bytes/pixel of area is required.
Polygon draw flag buffer
This area is used to perform polygon drawing hidden surfaces in 3D graphics drawing. 1bit/pixel of area is required. 1 line is aligned by byte to byte.
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6.2 Polygon Drawing
6.2.1 Drawing Primitives
MB86290A supports the following primitive types: - Point - Line - Triangle - Fast2DLine - Fast2Dtriangle - Polygon
6.2.2 Polygon Drawing
An irregular polygon (including concave shape) is drawn by dedicated hardware as follows:
1. 2.
Execute PolygonBegin command Initialize polygon draw enginew Draw vertices. Draw outline of polygon and plot all vertices to polygon draw flag buffer utilizing Fast2Dtriangle primitive. Execute PolygonEnd command. Copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern.
3.
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6.2.3 Drawing Parameters
MB86290A differentiates triangles (Right triangle and Left triangle) according to the locations of three vertices as follows (not used for Fast2Dtriangle):
V0 U p p e r s id e L o n g s id e U p p e r tria n g le V1 U p p e r s id e U p p e r tria n g le V1 L o n g s id e V0
L o w e r s id e V2 L o w e r tria n g le
L o w e r s id e L o w e r tria n g le
V2
R ig h t tria n g le
L e ft tria n g le
The following parameters are required for drawing triangles (For Fast2Dtriangle, X and Y coordinates of each vertex are specified).
Ys Xs,Zs,Rs,Gs,Bs,Ss,Ts,Qs XUs
Upper side start Y coordinate dXdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy dXUdy dZdx,dRdx,dGdx,dB dx, dSdx,dTdx,dQ dx USN
Low er side start Y coordinate XLs dXLdy LSN
Note:
Be careful about the positional relationship between coordinates Xs, XUs, and XLs. For example, in the above diagram, when a right-hand triangle is drawn using the parameter that shows the coordinates positional relationship Xs (upper edge start Y coordinate) > XUs or Xs (lower edge start Y coordinate) > XLs, the expected picture may not be drawn.
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Ys Xs XUs XLs Zs Rs Gs Bs Ss Ts Qs dXdy dXUdy dXLdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy USN LSN dZdx dRdx dGdx dBdx dSdx dTdx dQdx
Y-coordinate start position of long side X-coordinate start position of long side X-coordinate start position of upper side X-coordinate start position of lower side Z-coordinate start position of long side R value at (Xs, Ys, Zs) of long side G value at (Xs, Ys, Zs) of long side B value at (Xs, Ys, Zs) of long side S-coordinate of texture at (Xs, Ys, Zs) of long side T-coordinate of texture at (Xs, Ys, Zs) of long side Q (Perspective correction value) of texture at (Xs, Ys, Zs) of long side X DDA value of long side X DDA value of upper side X DDA value of lower side Z DDA value of long side R DDA value of long side G DDA value of long side B DDA value of long side S DDA value of long side T DDA value of long side Q DDA value of long side Number of spans (rasters) of top triangle Number of spans (rasters) of bottom triangle Z DDA value of horizontal way R DDA value of horizontal way G DDA value of horizontal way B DDA value of horizontal way S DDA value of horizontal way T DDA value of horizontal way Q DDA value of horizontal way
6.2.4 Anti-aliasing Function
MB86290A performs anti-aliasing to eliminate jaggies on line edges and make lines appear smooth. To use this function at the edges of primitives, redraw the primitive edges with anti-alias lines.
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6.3 Bit Map Operation
6.3.1 BLT
A rectangular shape in pixel units can be transferred between two separate physical memory areas as follows: (1) From host CPU to Drawing frame memory (2) From Graphics Memory (other than Drawing frame memory area) to drawing memory (3) From host CPU to internal texture memory (4) From Graphics Memory to internal texture memory When Drawing frame memory is designated as the destination, the result of logical calculation between the source and current value in the designated destination can be stored as well. If part of the source and destination of the BLT field are physically overlapped in the display frame, the start address (from which vertex the BLT field to be transferred) must be set carefully.
Usage caution: When transferring a rectangle from one graphics memory to another graphics memory (drawing frames included), or from the host CPU to the internal texture memory, the width of the rectangle must be at least 5 pixels (in direct color mode) or 9 pixels (in indirect color mode).
6.3.2 Pattern Data Format
MB86290A can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel), and binary bit map (1 bit/pixel). The direct color mode is used for texture patterns. Either the indirect or direct color mode is used for tiling patterns. The binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel, and background color is applied for bitmap = 0 pixels.
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6.4 Texture Mapping
Texture mapping is supported when the direct color mode (16 bits/pixel) drawing frame is used.
6.4.1 Texture Size
MB86290A reads texcel data from the specified texture coordinate (S, T) position, and pastes that data at the correlated pixel position of the polygon. The applicable texture data size is 16, 32, 64, 128 or 256 pixels per S and T, respectively. Texture mapping is used only when the direct color mode (16bit/pixel) is used.
6.4.2 Texture Memory
Texture pattern data is stored in either the MB86290A internal texture buffer or external Graphics Memory. The internal texture buffer size is 8 Kbyte and can hold up to 64 x 64 pixels of texture. If the texture pattern size is smaller than 64 x 64pixels, it is best to store it in the internal texture buffer because the texture mapping speed is faster.
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6.4.3 Texture Lapping
If a negative or larger than applicable value is specified as the texture coordinate (S, T), according to the setting, one of these options (repeat, cramp or border) is selected for the `out-of-range' texture mapping. The mapping image for each case is shown below:
Repeat
Repeat
Cramp
Border
This just masks the upper bits of the applied (S, T) coordinate and enables the lower bits of the coordinate within the specified texture pattern size. When the texture pattern size is 64 x 64pixels, it masks the upper bits of the integer part of (S, T) the coordinate and enables the lower 6 bits.
Cramp
When the applied (S, T) coordinate is either negative or larger than the specified texture pattern size, cramp the (S, T) coordinate as follows: S<0 S=0 S > Texture X size - 1 S = Texture X size - 1
Border
When the applied (S, T) coordinate is either negative or larger than the specified texture pattern size, the outside of the specified texture pattern is rendered in the `border' color.
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6.4.4 Filtering
MB86290A supports two texture filtering modes: point filtering, and bi-linear filtering.
Point filtering
This mode uses the texcel data specified by the (S, T) coordinate. The nearest texcel in the texture pattern is chosen according to the calculated (S, T) coordinate.
0. 0. 1. 1. 2.
0. 1. 1. 2.
Bi-linear filtering
This mode picks the four nearest texcels from the calculated (S, T) coordinate. The color is blended and the texcel image is defined according to the distance between each of these texcels and the calculated (S, T) coordinate.
Note: This mode can be used when the internal memory is specified as the texture memory mode.
0. 0. C0 0. 1. 1. 2.
1.
1.
2.
C1
C0
C1
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6.4.5 Perspective Correction
This function adjusts the depth distortion of the 3D projection in the texture mapping process. For this adjustment, the `Q' element of the texture coordinate (Q = 1/W) is defined from the 3D coordinate of the correlated vertex. This Q value is used after normalizing in the range between 0.0 and 1.0.
6.4.6 Texture Blending
MB86290A supports the following three texture blending modes:
Decal
This mode displays the mapped texcel color regardless the native polygon color.
Modulate
This mode multiplies the native polygon color (CP) and sampled texcel color (CR) and display the result (CO). C0 = CR x CP
Stencil
This mode uses the MSB to select the display color from the sampled texcel color. MSB = 1: Texcel color MSB = 0: Polygon color
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6.5 Rendering
6.5.1 Tiling
Tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. The tiling pixel is determined by the coordinate of the correlated pixel irrespective of the primitive position and size. Since the tiling pattern is stored in the internal texture buffer, this function and texture mapping cannot be used at the same time. Also, the tiling pattern size is limited to within 64 x 64 pixels.
Fig. 6.4 Example of Tiling Operation
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6.5.2 Alpha Blending
Alpha blending blends the pixel's native color and current color of that pixel position according to the blending ratio parameter set in the alpha register. This function cannot be used simultaneously with logical calculation. It can be used only when the direct color mode (16 bits/pixel) is used. The blended color C is calculated as shown below when the native color of the pixel to be rendered is CP, the current pixel color of that position is CF, and the alpha value set in the alpha register is A: C = CP x A + (1-A) x CF The alpha value is specified as 8-bit data. 00h means alpha value 0% and FFh means alpha value 100%. When the texture mapping function is enabled, the following blending modes are applicable:
Normal
Blends post texture mapping color with current frame buffer color
Stencil
Uses MSB of texcel color to select display color: MSB = 1: Texcel color MSB = 0: Current frame buffer color
Stencil alpha
Uses MSB of texcel color to select and activate alpha-blend function:
MSB = 1: Alpha blend texcel color and current frame buffer color
MSB = 0: Current frame buffer color
6.5.3 Logical Calculation
This mode executes a logical calculation between the new pixel color to be rendered and the current frame memory color and displays the result. Alpha blending cannot be used when this function is used.
Type CLEAR COPY NOP SET COPY INVERTED INVERT AND REVERSE OR REVERSE ID 0000 0011 0101 1111 1100 1010 0010 1011 Operation 0 S D 1 !S !D S & !D S | !D Type AND OR NAND NOR XOR EQUIV AND INVERTED OR INVERTED ID 0001 0111 1110 1000 0110 1001 0100 1101 Operation S&D S|D !(S & D) !(S | D) S xor D !(S xor D) !S & D !S | D
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6.5.4 Hidden Surface Management
This function compares the Z value of a new pixel to be rendered and the existing Z value in the Z buffer. Display/not display is switched according to the Z-compare mode setting. Define the Z-buffer access options in the ZWRITEMASK mode. The Z-comparison type is determined by the Z compare mode.
ZWRITEMASK
1 0
Compare Z values, no Z buffer overwrite Compare Z values and overwrite result to Z buffer
Z Compare mode NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL
ID 000 001 010 011 100 101 110 111
Condition Never draw Always draw Draw if pixel Z value < current Z buffer value Draw if pixel Z value < current Z buffer value Draw if pixel Z value = current Z buffer value Draw if pixel Z value < current Z buffer value Draw if pixel Z value > current Z buffer value Draw if pixel Z value < current Z buffer value
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6.6 Drawing Attributes
6.6.1 Line Draw Attributes
When line draw operations are performed, the following attributes apply: Line Draw Attributes Attribute Line Width Broken Line Draw Anti-alias Description Line width selectable in range of 1-32 pixels Specify broken line pattern in 32-bit data Line edge smoothed when anti-aliasing enabled
6.6.2 Triangle Draw Attributes
When triangle draw operations are performed, the following attributes apply. Texture mapping and tiling have separated texture attributes: Triangle Draw Attributes Attribute Shading Alpha blending Blending parameter Description Gouraud shading or flat shading selectable Set alpha blend enable per polygon Set color blend ratio of alpha blend
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6.6.3 Texture Attributes
The following attributes apply for texture mapping: Texture Attributes Attribute Texture mode Texture memory mode Texture filter Texture coordinate correction Texture wrap Texture blend mode Description Select either texture mapping or tiling Select either internal texture buffer or external Graphics Memory to use in texture mapping Select either point sampling or bi-linear filtering The bilinear filter can be specified when the internal memory is specified as the texture memory mode. Select either linear or perspective correction Select either repeat or cramp of texture pattern Select either decal or modulate
6.6.4 Character/Font Drawing and BLT Attributes
When character/font pattern draw and BLT draw are performed, the following attributes apply: Character/Font Pattern and BLT Attributes Attribute Character pattern enlarge/shrink Character pattern color Logical calculation mode Description 2 x 2, x 2 horizontal, 1/2 x 1/2, x 1/2 horizontal Set character color and background color Specify two source logical calculation mode in BLT operation
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6.7 Display List
6.7.1 Overview
Display list is a set of display list commands, parameters and pattern data. All display list commands in a display list are executed consequently (Note that display list command does not mean draw command). The display list is transferred to the display list FIFO by one of the following methods: CPU write to display FIFO DMA transfer from main memory to display FIFO Register set to transfer from graphics memory to display FIFO
Display list Command-1 Data 1-1 Data 1-2 Data 1-3 Display list Command-2 Data 2-1 Data 2-2 Data 2-3 -----Display List
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6.7.2 Header Format
Format Overview
Format Format 1 Format 2 Format 3 Format 4 Format 5 Format 6 Format 7 Format 8 Format 9 31 Type Type Type Type Type Type Type Type Type 24 23 Reserved Count Reserved Reserved Draw Command Draw Command Draw Command Draw Command Reserved 16 15 Reserved Address Reserved Reserved Reserved Count Reserved Reserved Reserved Flag Flag Vertex Vertex Flag Vertex Vertex 0
Description of Each Field Type DrawCommand Count Address Vertex Flag Display list type Draw command Number of parameters excluding header Address value used at data transfer Vertex number Dedicated attribute flag of display list command
Vertex Number Specified in Vertex Code Vertex 00 01 10 11 Vertex number (Line) V0 V1 Inhibited Inhibited Vertex number (Triangle) V0 V1 V2 Inhibited
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6.7.3 Display List Command Overview
The following table lists the MB86290A display list commands. Type Nop Interrupt Sync SetRegister SetVertex2i Draw Command Normal PolygonBegin PolygonEnd Draw Flush_FB/Z All draw commands Pixel PixelZ Xvector Yvector AntiXvector AntiYvector ZeroVector OneVector TrapRight TrapLeft TriangleFan FlagTriangleFan BltFill ClearPolyFlag BltDraw Bitmap TopLeft TopRight BottomLeft BottomRight LoadTexture LoadTILE LoadTexture LoadTILE Description No operation Interrupt request to host CPU Synchronization of events Data set to register Data set to Fast2DTriangle VRTX register Initialization of border rectangle calculation of multiple vertices random shape Polygon flag clear (post random shape drawing operation) Flushes drawing pipelines Issue draw command Plot Point Plot Point with Z value Draw Line (*1) Draw Line (*2) Draw Line with anti-alias option (*1) Draw Line with anti-alias option (*2) Draw Fast2DLine (start from vertex 0) Draw Fast2DLine (start from vertex1) Draw Right Triangle Draw Left Triangle Draw Fast2DTriangle Draw Fast2DTriangle for multiple vertices random shape Fill rectangle with one color or tiling pattern Clear Polygon flag buffer Draw rectangle pattern Draw binary bit map pattern (character) BitBlt transfer from left upper vertex BitBlt transfer from right upper vertex BitBlt transfer from left lower vertex BitBlt transfer from right lower vertex Load texture pattern Load tile pattern Load texture pattern from Graphics Memory Load tile pattern from Graphics Memory
DrawPixel DrawPixelZ
DrawLine
DrawLine2I DrawLine2iP DrawTrap DrawVertex2i DrawVertex2iP DrawRect DrawRectP DrawBitmap DrawBitmapP BltCopy BltCopyP BltCopy Alternate BltCopy AlternateP LoadTexture BltTexture Note
(*1) -Pai/4 Line angle Pai/4 (*2) -Pai/2 Line angle -Pai/4, or Pai/4 Line angle Pai/2
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Type Field Code Table Type DrawPixel DrawPixelZ DrawLine DrawLine2i DrawLine2iP DrawTrap DrawVertex2i DrawVertex2iP DrawRectP DrawBitmapP BitCopyP BitCopyAlternateP LoadTextureP BltTextureP SetVertex2i SetVertex2iP Draw SetRegister Sync Interrupt Nop 0000_0000 0000_0001 0000_0010 0000_0011 0000_0100 0000_0101 0000_0110 0000_0111 0000_1001 0000_1011 0000_1101 0000_1111 0001_0001 0001_0011 0111_0000 0111_0001 1111_0000 1111_0001 1111_1100 1111_1101 1111_1111 Code
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Draw Command Code Table (1) DrawCommand Pixel PixelZ Xvector Yvector XvectorNoEnd YvectorNoEnd XvectorBlpClear YvectorBlpClear XvectorNoEndBlpClear YvectorNoEndBlpClear AntiXvector AntiYvector AntiXvectorNoEnd AntiYvectorNoEnd AntiXvectorBlpClear AntiYvectorBlpClear AntiXvectorNoEndBlpClear AntiYvectorNoEndBlpClear ZeroVector Onevector ZeroVectorNoEnd OnevectorNoEnd ZeroVectorBlpClear OnevectorBlpClear ZeroVectorNoEndBlpClear OnevectorNoEndBlpClear AntiZeroVector AntiOnevector AntiZeroVectorNoEnd AntiOnevectorNoEnd AntiZeroVectorBlpClear AntiOnevectorBlpClear AntiZeroVectorNoEndBlpClear AntiOnevectorNoEndBlpClear 000_00000 000_00001 001_00000 001_00001 001_00010 001_00011 001_00100 001_00101 001_00110 001_00111 001_01000 001_01001 001_01010 001_01011 001_01100 001_01101 001_01110 001_01111 001_10000 001_10001 001_10010 001_10011 001_10100 001_10101 001_10110 001_10111 001_11000 001_11001 001_11010 001_11011 001_11100 001_11101 001_11110 001_11111 Code
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Draw Command Code Table (2) DrawCommand BltFill BltDraw Bitmap TopLeft TopRight BottomLeft BottomRight LoadTexture LoadTILE TrapRight TrapLeft TriangleFan FlagTriangleFan Flush_FB Flush_Z PolygonBegin PolygonEnd ClearPolyFlag Normal 010_00001 010_00010 010_00011 010_00100 010_00101 010_00110 010_00111 010_01000 010_01001 011_00000 011_00001 011_00010 011_00011 110_00001 110_00010 111_00000 111_00001 111_00010 111_11111 Code
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6.7.4 Details of Display List Commands
All parameters belonging to their command are set in correlated registers. The definition of each parameter is figured out in the section of each command description. Nop (Format1)
31 Nop 24 23 Reserved 16 15 Reserved 0
No operation
Interrupt (Format1)
31 Interrupt 24 23 Reserved 16 15 Reserved 0
Generates interrupt request to host CPU
Sync (Format9)
31 Sleep 24 23 Reserved 16 15 Reserved 4 flag 0
Suspends all subsequent display list operations until event specified in Flag field detected
Flag:
Bit # Bit field name 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 VBLANK
Bit0
VBLANK VBLANK Synchronization 0 1 No operation Wait for VSYNC detection
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SetRegister (Format2)
31 SetRegister 24 23 Count (Val 0) (Val 1) --(Val n) 16 15 Address 0
Sets data at consecutive registers
Count:
Data word count (in double-word unit)
Address:
Register address Set the register address as the byte address/4 (address in doubleword units).
SetVertex2i (Format8)
31 SetVertex2i Xdc Ydc 24 23 Draw Command 16 15 Reserved 4 3 flag 2 1 0 vertex
Sets vertices data for Fast2DLine or Fast2DTriangle command at registers
Commands:
Normal PolygonBegin Set vertex data (X, Y). Start calculation of circumscribed rectangle for random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd.
Flag: Not used
SetVertex2iP (Format8)
31 SetVertex2i Ydc 24 23 Draw Command 16 15 Reserved Xdc 4 3 flag 2 1 0 vertex
Sets vertices data for Fast2DLine or Fast2DTriangle command to registers
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Only the packed integer format can be used specify these vertices. Command:
Normal PolygonBegin Set vertices data. Start calculation of circumscribed rectangle of random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd.
Flag: Not used
Draw (Format5)
31 Draw 24 23 Draw Command 16 15 Reserved 0
Executes draw command All parameters required at execution of a draw command must be set at their appropriate registers.
Commands:
PolygonEnd Draw random shape of multiple vertices. Fill random shape with color according to flags generated by FlagTriangleFan command and information of circumscribed rectangle generated by PolygonBegin command. Flush_FB Flush_Z This command flushes drawing data in the drawing pipeline into the graphics memory. Place this command at the end of the display list. This command flushes Z-value data in the drawing pipeline into the graphics memory. When using the Z buffer, place this command together with the Flush_FB command at the end of the display list.
DrawPixel (Format5)
31 DeawPixel PXs PYs 24 23 Draw Command 16 15 Reserved 0
Plots pixel
Command:
Pixel Plot pixel (without Z value).
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DrawPixelZ (Format5)
31 DeawPixel PXs PYs PZs 24 23 Draw Command 16 15 Reserved 0
Plots 3D pixel
Command:
PixelZ Plot pixel (with Z value).
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DrawLine (Format5)
31 DrawLine 24 23 Draw Command LPN LXs LXde LYs LYde 16 15 Reserved 0
Draws line Start drawing after setting all parameters at line draw registers.
Commands:
Xvector Yvector XvectorNoEnd YvectorNoEnd XvectorBlpClear YvectorBlpClear XvectorNoEndBlpClear YvectorNoEndBlpClear AntiXvector AntiYvector AntiXvectorNoEnd AntiYvectorNoEnd AntiXvectorBlpClear AntiYvectorBlpClear AntiXvectorNoEndBlpClear AntiYvectorNoEndBlpClear Draw line (*1). Draw line (*2). Draw line without end point (*1). Draw line without end point (*2). Draw line (*1). Prior to drawing, clear reference position of broken line pattern. Draw a line (*2) Prior to drawing, clear reference position of broken line pattern. Draw line without end point (*1). Prior to drawing, clear reference position of broken line pattern. Draw line without end point (*2). Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line (*1). Draw anti-alias line (*2). Draw anti-alias line without end point (*1). Draw anti-alias line without end point (*2). Draw anti-alias line (*1). Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line (*2). Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line without end point (*1). Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line without end point (*2). Prior to drawing, clear reference position of broken line pattern
Note Pai/2
(*1) -Pai/4 Line angle Pai/4 (*2) -Pai/2 Line angle -Pai/4, orPai/4 Line angle
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DrawLine2i (Format7)
31 DrawLine2i LFXs LFYs 24 23 Draw Command 16 15 Reserved 0 0 0 Vertex
Draws Fast2Dline Start drawing after setting parameters at the Fast2DLIne draw registers. Integer data can only be used for vertices.
Commands:
ZeroVector OneVector ZeroVectorNoEnd OneVectorNoEnd ZeroVectorBlpClear OneVectorBlpClear ZeroVectorNoEndBlpClear OneVectorNoEndBlpClear AntiZeroVector AntiOneVector AntiZeroVectorNoEnd AntiOneVectorNoEnd AntiZeroVectorBlpClear AntiOneVectorBlpClear AntiZeroVectorNoEndBlpClear AntiOneVectorNoEndBlpClear Draw line from vertex 0 to vertex 1. Draw line from vertex 1 to vertex 0. Draw line without end point from vertex 0 to vertex 1. Draw line without end point from vertex 1 to vertex 0. Draw line from vertex 0 to vertex 1. Prior drawing, clear reference position of broken line pattern. Draw line from vertex 1 to vertex 0. Prior to drawing, clear reference position of broken line pattern. Draw line from vertex 0 to vertex 1 without end point. Prior to draw, clear reference position of broken line pattern. Draw line from vertex 1 to vertex 0 without end point. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 0 to vertex 1. Draw anti-alias line from vertex 1 to vertex 0. Draw anti-alias line without end point from vertex 0 to vertex 1. Draw anti-alias line without end point from vertex 1 to vertex 0. Draw anti-alias line from vertex 0 to vertex 1. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 1 to vertex 0. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 0 to vertex 1 without end point. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 1 to vertex 0 without end point. Prior to drawing, clear reference position of broken line pattern.
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DrawLine2iP (Format7)
31 DrawLine2iP LFYs 24 23 Draw Command 16 15 Reserved LFXs 0 Vertex
Draws Fast2Dline Start drawing after setting parameters at Fast2DLIne draw registers. Only packed integer data can be used for vertices.
Commands:
ZeroVector OneVector ZeroVectorNoEnd OneVectorNoEnd ZeroVectorBlpClear OneVectorBlpClear ZeroVectorNoEndBlpClear OneVectorNoEndBlpClear AntiZeroVector AntiOneVector AntiZeroVectorNoEnd AntiOneVectorNoEnd AntiZeroVectorBlpClear AntiOneVectorBlpClear AntiZeroVectorNoEndBlpClear AntiOneVectorNoEndBlpClear Draw line from vertex 0 to vertex 1. Draw line from vertex 1 to vertex 0. Draw line without end point from vertex 0 to vertex 1 Draw line without end point from vertex 1 to vertex 0 Draw line from vertex 0 to vertex 1. Prior to drawing, clear the reference position of the broken line pattern. Draw line from vertex 1 to vertex 0. Prior to drawing, clear reference position of broken line pattern. Draw line from vertex 0 to vertex 1 without end point. Prior to drawing, clear reference position of broken line pattern. Draw line from vertex 1 to vertex 0 without end point. Prior to drawing, clear reference position of te broken line pattern. Draw anti-alias line from vertex 0 to vertex 1. Draw anti-alias line from vertex 1 to vertex 0. Draw anti-alias line without end point from vertex 0 to vertex 1. Draw anti-alias line without end point from vertex 1 to vertex 0. Draw anti-alias line from vertex 0 to vertex 1. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 1 to vertex 0. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 0 to vertex 1 without end point. Prior to drawing, clear reference position of broken line pattern. Draw anti-alias line from vertex 1 to vertex 0 without end point. Prior to drawing, clear reference position of broken line pattern.
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DrawTrap (Format5)
31 DrawTrap Ys Xs DXdy XUs DXUdy XLs DXLdy USN LSN 0 0 24 23 Draw Command 16 15 Reserved 0 0
Draws Triangle Operation is started after setting all the related parameters at the Plane Draw registers.
Commands:
TrapRight TrapLeft Draw Right Triangle. Draw Left Triangle.
DrawVertex2i (Format7)
31 DrawVertex2i Xdc Ydc 24 23 Draw Command 16 15 Reserved 0 0 0 Vertex
Draws Fast2Dtriangle Operation is started after setting all the related parameters at the Plane Draw registers.
Commands:
TriangleFan FlagTriangleFan Draw Fast2Dtriangle. Draw Fast2DTriangle for random shape with multiple vertices.
DrawVertex2iP (Format7)
31 DrawVertex2iP Ydc 24 23 Draw Command 16 15 Reserved Xdc 0 Vertex
Draws Fast2Dtriangle
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Operation is started after setting all the related parameters at Plane Draw registers Only the packed integer format can be used for vertex coordinates.
Commands:
TriangleFan FlagTriangleFan Draw Fast2Dtriangle. Draw Fast2DTriangle for random shape with multiple vertices.
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DrawRectP (Format5)
31 DrawRectP RYs RsizeY 24 23 Draw Command 16 15 Reserved RXs RsizeX 0
Fills rectangle The designated rectangle is filled with the current color after setting all the related parameters at the rectangle registers.
Commands:
BltFill ClearPolyFlag Fill rectangle with current color (single) or current tiling pattern. Fill polygon flag field with 0. The size is defined in RsizeX,Y.
DrawBitmapP (Format6)
31 DrawBitmapP RYs RsizeY (Pattern 0) (Pattern 1) --(Pattern n) 24 23 Draw Command 16 15 Count RXs RsizeX 0
Draws rectangle
Commands:
BltDraw DrawBitmap Draw rectangle of 8 bits/pixel or 16 bits/pixel. Draw binary bitmap character pattern. Bit0 is drawn in transparent or background color, and bit1 is drawn in foreground color. Background color is specified in the BC register, and foreground color is specified in the FC register.
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BltCopyP (Format5)
31 BltCopyP SRYs DRYs BRsizeY 24 23 Draw Command 16 15 Reserved SRXs DRXs BRsizeX 0
Copies rectangle pattern within one drawing frame For BRsizeX, specify at least 5 pixels (when direct color mode used) or 9 pixels (when indirect color mode used).
Commands:
TopLeft TopRight BottomLeft BottomRight Start BitBlt transfer from top left vertex. Start BitBlt transfer from top right vertex. Start BitBlt transfer from bottom left vertex. Start BitBlt transfer from bottom right vertex.
BltCopyAlternateP (Format5)
31 BltCopyAlternateP 24 23 Draw Command SADDR SStride SRYs DADDR DStride DRYs BRsizeY DRXs BRsizeX SRXs 16 15 Reserved 0
Copies rectangle between two separate drawing frames For BRsizeX, specify at least 5 pixels (when direct color mode used) or 9 pixels (when indirect color mode used).
Commands:
TopLeft Start BitBlt transfer from top left vertex.
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LoadTextureP (Format6)
31 LoadTextureP 24 23 Draw Command (Pattern 0) (Pattern 1) --(Pattern n) 16 15 Count 0
Loads texture or tile pattern into internal texture buffer memory Supply a texture pattern to the internal texture buffer according to the current pattern size (TXS/TIS) and offset address (XBO).
Commands:
LoadTexture LoadTile Load texture pattern to internal texture buffer. Load tile pattern to internal texture buffer.
BltTextureP (Format5)
31 BltTextureP 24 23 Draw Command SrcADDR SrcStride SrcRectYs BRsizeY DestOffset SrcRectXs BRsizeX 16 15 Reserved 0
Loads texture or tile pattern into internal texture buffer memory from Graphics Memory Supply a texture pattern to the internal texture buffer according to current pattern size (TXS/TIS) and offset address (XBO). For DestOffset, specify the word-aligned byte address (16 bits) (bit 0 is always 0). For BRsizeX, specify at least 5 pixels (when direct color mode used) or 9 pixels (when indirect color mode used).
Commands:
LoadTexture LoadTile Load texture pattern into internal texture buffer. Load tile pattern into internal texture buffer.
92
7 Registers
7.1 Description
All the terms in this chapter are explained below:
(1) Register address Indicates address of register (2) Bit # Indicates bit number (3) Bit field name Indicates name of each bit field in register (4) R/W Indicates access attribute (Read/Write) of each field Each sign shown in this section means the following: R0 W0 R RX RW RW0 (5) Default This section shows the reset defaults for each bit field. 0 always read at read. Write access is Don't care. Only 0 can be written Enable read Enable read (read values undefined) Enable read and write any data Enable read and write 0
93
7.1.1 Host Interface Registers
DTC (DMA Transfer Count)
Register address Bit #
HostBaseAddress + 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved R0 0 DTC RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
DTCR is a 32-bit wide register to set the DMA data transfer count to either one long-word (32 bits) or eight long-word (32 bytes) units. This register is read/write enabled. When 1h is set, one data unit is transferred by DMA. However, when 0h is set, it indicates the maximum transfer data count and 16M (16,777,216) data units are transferred. After DMA transfer is started, the register value cannot be overwritten until DMA transfer is completed. Note: In the V832 mode, no setting is required for this register.
DSU (DMA Set Up)
Register address Bit # HostBaseAddress + 04h 7 6 5 Reserved R0 0 4 3 2 DAM RW 0 1 DBM RW 0 0 DW RW 0
Bit field name R/W Default
Bit0
DW(DMA Word) Sets DMA transfer unit 0 1 1 long words (32 bytes) per DMA transaction 8 long word (32 bits) per DMA transaction (only SH4)
Bit1
DBM (DMA Bus request Mode) Selects DREQ mode used when performing DMA transfer in dual-address mode 0 DREQ is irrelevant to the cycle steal mode or burst mode, and is not negated during DMA transfer. 1 DREQ is irrelevant to the cycle steal mode or burst mode, and is negated when the MB86290A cannot receive data (that is, when Ready cannot be returned immediately). When the MB86290A is ready to receive data, DREQ is reasserted (When DMA transfer is performed in the single-address mode, DREQ is controlled automatically). DAM(DMA Address Mode) Sets DMA addressing mode 0 1 Dual address mode Single address mode (SH4 only)
Bit2
94
DRM (DMA Request Mask)
Register address Bit # HostBaseAddress + 05h 7 6 5 4 Reserved R0 0 3 2 1 0 DRM RW 0
Bit field name R/W Default
This register controls the DMA request to the host CPU. Setting 1 at this register tentatively masks the DMA request. The DMA request is restarted when 0 is set at this register.
DST (DMA STatus)
Register address Bit # HostBaseAddress + 06h 7 6 5 4 Reserved R0 0 3 2 1 0 DST R 0
Bit field name R/W Default
This register indicates the DMA status. DST is set to 1 during DMA transfer. This state is cleared to 0 when the DMA transfer is completed.
DTS (DMA Transfer Stop)
Register address Bit # HostBaseAddress + 08h 7 6 5 4 Reserved R0 0 3 2 1 0 DTS RW 0
Bit field name R/W Default
This register suspends DMA transfer. An ongoing DMA transfer is suspended by setting DTS to 1.
LSTA (displayList transfer STAtus)
Register address Bit # HostBaseAddress + 10h 7 6 5 4 Reserved R0 0 3 2 1 0 LSTA R 0
Bit field name R/W Default
95
This register indicates the DisplayList transfer status from Graphics Memory. LSTA is set to 1 while DisplayList transfer is in progress. This status is cleared to 0 when DisplayList transfer is completed
DRQ (DMA ReQquest)
Register address Bit # HostBaseAddress + 18h 7 6 5 4 Reserved R0 0 3 2 1 0 DRQ RW1 0
Bit field name R/W Default
Starts sending external DMA request signal DMA transfer using the external DMA request handshake is triggered by setting DRQ to 1. The external DREQ signal is not asserted when DMA is masked by the DRM register. This register cannot be set to 0. When DMA transfer is completed, this status is cleared automatically to 0.
IST (Interrupt STatus)
Register address Bit # HostBaseAddress + 20h 7 6 Reserved R0 0 5 4 FSYNC RW0 0 3 SYNCERR RW0 0 2 VSYNC RW0 0 1 CEND RW0 0 0 CERR RW0 0
Bit field name R/W Default
This register indicates the current interrupt status. When an interrupt request to the host CPU is asserted, this register displays 1. The interrupt status is cleared by setting 0 at this register.
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
CERR (Command Error Flag) Draws command execution error interrupt CEND (Command END) Draws command complete interrupt VSYNC (Vertical Sync.) VSYNC detection interrupt FSYNC (Frame Sync.) Indicates frame synchronization interrupt SYNCERR (Sync. Error) Indicates external synchronization error interrupt
96
IMASK (Interrupt MASK)
Register address Bit # HostBaseAddress + 24h 7 6 Reserved R0 0 5 4 SYNCERRM RW 0 3 FSYNCM RW 0 2 VSYNCM RW 0 1 CENDM RW 0 0 CERRM RW 0
Bit field name R/W Default
This register masks interrupt requests. When the flag is set to 1, the respective event is masked so that no interrupt request is asserted to the host CPU when an event occurs.
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 CERRM (Command Error Interrupt Mask) Masks draw command execution error interrupt CENDM (Command Interrupt Mask) Masks draw command complete interrupt VSYNCM (Vertical Sync. Interrupt Mask) Masks VSYNC detection interrupt FSYNCM (Frame Sync. Interrupt Mask) Masks frame synchronization interrupt SYNCERRM (Sync. Error Interrupt Mask) Masks external synchronization error interrupt
SRST (Software ReSeT)
Register address Bit # HostBaseAddress + 2Ch 7 6 5 4 Reserved R0 0 3 2 1 0 SRST W1 0
Bit field name R/W Default
This register controls software reset. When 1 is set at this register, a software reset is issued. LSA (displayList Source Address)
Register address Bit # HostBaseAddress + 40h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved R0 0 RW Don't care LSA R0 0 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register sets the DisplayList transfer source address. When DisplayList is transferred from Graphics Memory, set the List start address. Since the lowest two bits of this register are always set to 0, DisplayList must be 4-byte aligned. The contents set at this register do not change until another value is set.
97
LCO (displayList Count)
Register address Bit # HostBaseAddress + 44h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved R0 0 LCO RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register sets the DisplayList. transfer word count. When 1 is set, 1-word data is transferred. When 0 is set, it is considered to be the maximum number and 16M (16,777,216) words of data are transferred. The contents set at this register do not change until another value is set. LREQ (displayList transfer REQuest)
Register address Bit # HostBaseAddress + 48h 7 6 5 4 Reserved R0 0 3 2 1 0 LREQ RW1 0
Bit field name R/W Default
This register triggers DisplayList transfer from the Graphics Memory. Transfer is started by setting LREQ to 1. DisplayList. The DisplayList is transferred from the Graphics Memory to the internal display list FIFO. Access to the display list FIFO by the CPU or DMA is prohibited while this transfer is in progress.
7.1.2 Graphics Memory Interface Registers
MMR (Memory I/F Mode Register)
Register address Bit # HostBaseAddress + FFFCh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve W0 00 RX Don't care TRRD RW 11 TRC RW 1001 TRP RW 11 TRAS RW 110 TRCD LOWD RW 11 RW 10 8 7 6 5 4 3
ASW RW
2
1 CL RW 011
0
Bit field name R/W Default
RTS RW 0111
RAW RW 10
1
This register controls the graphics memory interface mode setting. An appropriate value must be set at this register after reset (even if the default value is used). This register is not initialized by a software reset.
Bits 2-0
CL (CAS Latency) Set CAS latency cycles. Set same value at mode register of SDRAM. 011 010 Others CL3 CL2 Prohibited
98
Bit 3
ASW (Attached SDRAM bit Width) Sets data bus width of Graphics Memory interface 1 0 64 bit 32 bit
Bits 5-4
RAW (Row Address Width) Set bit width of Row address 00 11 Others 14 bit 13 bit Prohibited
Bits 9-6
RTS (Refresh Timing Setting) Set refresh interval 1010 1001 1000 0111 Others 1024 clocks 512 clocks 256 clocks 128 clocks Prohibited
99
Bits 11-10
LOWD Set last data output to next write command input latency 10 Others 2 clocks Prohibited
Bits 13-12
TRCD Set Bank Active to CAS latency 11 10 Others 3 clocks 2 clocks Prohibited
Bits 16-14
TRAS Set minimum Bank Active cycle 111 110 101 Others 7 clocks 6 clocks 5 clocks Prohibited
Bits 18-17
TRP Set Precharge to Bank Active wait time 11 10 Others 3 clocks 2 clocks Prohibited
Bits 22-19
TRC Set refresh to Bank Active wait time 1010 1001 1000 0111 Others 10 clocks 9 clocks 8 clocks 7 clocks Prohibited
Bits 24-23
TRRD Set Bank Active to next Bank Active wait time 11 10 Others 3 clocks 2 clocks Prohibited
100
7.1.3 Display Control Register
DCM (Display Control Mode)
Register address Bit # DisplayBaseAddress + 00h 15 CKS RW 0 14 13 12 11 10 SC RW 11110 9 8 7 6 5 EO RW 0 4
Reserve
3 SOF RW 0
2 ESY RW 0
1 SYNC RW 00
0
Bit field name R/W Default
Reserve R0 00
Reserve R0 00
R0 0
This register controls the display mode. It is not initialized by a software reset.
Bits 1-0
SYNC (Synchronize) Set synchronization mode X0 11 Non-interlace mode Interlace video mode
Bit 2
ESY (External Synchronize) Sets external synchronization mode 0 1 Disable Enable
Bit 3
SF (Synchronize signal output format) Sets active level of synchronization (VSYNC, HSYNC, CSYNC) signals 0 1 Low active High active
Bit 5
EO (Even/Odd signal mode) Defines EO signal output format 0 1 Low level output at even frame, High level output at odd frame High level output at even frame, Low level output at odd frame
Bits 12-8
SC (Scaling) Define pre-scaling ratio to generate dot clock 00000 00001 00010 : 11110 11111 No pre-scaling 1/2 1/3 : 1/31 (default) 1/32
Bit 15
CKS (Clock Source) Selects source clock 0 1 Internal PLL output clock DCLKI input
101
DCE (Display Controller Enable)
Register address Bit # DisplayBaseAddress + 02h 15 DEN RW 0 14 13 12 11 10 9 Reserved R0 0 8 7 6 5 4 3 BE RW 0 2 ME RW 0 1 WE RW 0 0 CE RW 0
Bit field name R/W Default
This register controls the video signal output and enables display of each layer.
Bit 0
CE (C layer Enable) Enables C-layer display 0 1 Does not display C layer Displays C-layer
Bit 1
WE (W layer Enable) Enables W-layer display 0 1 Does not display W-layer Displays W layer
Bit 2
ME (M layer Enable) Enables M layer display 0 1 Does not display M layer Displays M layer
Bit 3
BE (BL-layer Enable) Enables ML-layer display 0 1 Does not display B layer Displays B layer
Bit 15
DEN (Display Enable) Enables display 0 1 Does not output display signal Outputs display signal
102
HTP (Horizontal Total Pixels)
Register address Bit # DisplayBaseAddress + 06h 15 14 13 12 11 10 9 8 7 6 HTP RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the total pixel count. Setting + 1 is the total pixel count. HDP (Horizontal Display Period)
Register address Bit # DisplayBaseAddress + 08h 15 14 13 12 11 10 9 8 7 6 HDP RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the total horizontal display period in pixel clock units. Setting + 1 is the pixel count for the display period. HDB (Horizontal Display Boundary)
Register address Bit # DisplayBaseAddress + 0Ah 15 14 13 12 11 10 9 8 7 6 HDB RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the display period of the left partition in pixel raster units Setting + 1 is the pixel count for the display period of the left partition. When the screen is not partitioned into right and left before display, set the same value as HDP. HSP (Horizontal Synchronize pulse Position)
Register address Bit # DisplayBaseAddress + 0Ch 15 14 13 12 11 10 9 8 7 6 HSP RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the HSYNC pulse position in pixel clock unit. When the clock count since the start of the display period reaches Setting + 1, the horizontal synchronization signal is asserted.
103
HSW (Horizontal Synchronize pulse Width)
Register address Bit # DisplayBaseAddress + 0Eh 7 Reserved R0 0 6 5 4 3 HSW RW Don't care 2 1 0
Bit field name R/W Default
This register controls the HSYNC pulse width in pixel-clock units. Setting + 1 is the pulse width clock count. VSW (Vertical Synchronize pulse Width)
Register address Bit # DisplayBaseAddress + 0Fh 7 Reserved R0 0 6 5 4 3 VSW RW Don't care 2 1 0
Bit field name R/W Default
This register controls the VSYNC pulse width in raster units. Setting + 1 is the pulse width raster count. VTR (Vertical Total Rasters)
Register address Bit # DisplayBaseAddress + 12h 15 14 13 12 11 10 9 8 7 6 VTR RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the total raster count. Setting + 1 is the total raster count. For the interlace display, Setting + 1.5 is the total raster count for 1 field; 2 x setting + 3 is the total raster count for 1 frame (see Section 8.3.2). VSP (Vertical Synchronize pulse Position)
Register address Bit # DisplayBaseAddress + 14h 15 14 13 12 11 10 9 8 7 6 VSP RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the VSYNC pulse position in raster units. The vertical synchronization pulse is asserted starting at the Setting + 1-th raster relative to the display start raster.
104
VDP (Vertical Display Period)
Register address Bit # DisplayBaseAddress + 16h 15 14 13 12 11 10 9 8 7 6 VTR RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the vertical display period in raster unit. Setting + 1 is the count of rasters to be displayed. WX (Window position X)
Register address Bit # DisplayBaseAddress + 18h 15 14 13 12 11 10 9 8 7 6 WX RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the horizontal position of the left edge of the Window layer. Set the left edge position of the Window layer from the display field start edge in dot-clock units. WY (Window position Y)
Register address Bit # DisplayBaseAddress + 1Ah 15 14 13 12 11 10 9 8 7 6 WY RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the vertical position of the top edge of the Window layer. Set the top edge position of the Window layer from the display field start edge in raster units. WW (Window Width)
Register address Bit # DisplayBaseAddress + 1Ch 15 14 13 12 11 10 9 8 7 6 WW RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the horizontal size (pixel count) of the Window layer. Do not specify 0.
105
WH (Window Height)
Register address Bit # DisplayBaseAddress + 1Eh 15 14 13 12 11 10 9 8 7 6 WH RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the vertical height (raster count) of the Window layer. Setting + 1 is the height. CM (C-layer Mode)
Register address Bit # DisplayBaseAddress + 20h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
CC Reserve RW R0
8
7
6
5
4
3
2
1
0
Bit field name R/W Default
Reserve R0 0
CW RW Don't care
Reserve R0 0
CH RW Don't care
0
0
Bits 11-0
CH (C-layer Height) Set height of Console layer logical frame size in raster units. Setting + 1 is the height.
Bits 23-16
CW (C-layer memory Width) Set width of Console layer logical frame size in 64-byte units
Bit 31
CC (C-layer Color mode) Sets color mode used for Console layer 0 1 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel)
COA(C-layer Origin Address)
Register address Bit # DisplayBaseAddress + 24h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care COA R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame of the Console layer. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned.
106
CDA (C-layer Display Address)
Register address Bit # DisplayBaseAddress + 28h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 CDA RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the display field of the Console layer. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. CDX (C-layer Display position X)
Register address Bit # DisplayBaseAddress + 2Ch 15 14 13 12 11 10 9 8 7 6 CDX RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
Set the display start position (X-coordinate) for the C layer in pixel units relative to the origin of the logical frame. CDY (C-layer Display position Y)
Register address Bit # DisplayBaseAddress + 2Eh 15 14 13 12 11 10 9 8 7 6 CDY RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
Set the display start position (Y-coordinate) for the C-layer in pixel units relative to the origin of the logical frame. WM (W-layer Mode)
Register address Bit # DisplayBaseAddress + 30h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 WW RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
Reserve R0 0
Bits 21-16
WW(W-layer memory Width) Set width of Window layer logical frame size in 64-byte units. WC (W-layer Color mode) Sets color mode for W-layer 0 1 Indirect color (8 bits/pixel) mode Direct color (16 bits/pixel) mode
Bit 31
107
WOA (W-layer Origin Address)
Register address Bit # DisplayBaseAddress + 34h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care WOA R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame of the Window layer. Since the lowest 4-bits are fixed to 0, this address is 16-byte aligned. WDA (W-layer Display Address)
Register address Bit # DisplayBaseAddress + 38h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 WDA RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the display field of the Window layer. Since only the direct color mode is applicable to the Window layer, the LSB is fixed to 0 and this address is 2-byte aligned. MLM (ML-layer Mode)
Register address Bit # DisplayBaseAddress + 40h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MLC RW
8
7
6
5
4
3
2
1
0
Bit field name R/W Default
MLFLP
Reserve R0 0
MLW RW Don't care
Reserve R0 0
MLH RW Don't care
R0 0
0
Bits 11-0
MLH (ML-layer Height) Set height of Middle Left (ML) layer logical frame size in raster units. Setting + 1 is the height.
Bits 23-16
MLW (ML-layer memory Width) Set width of Middle Left (ML) layer logical frame size in 64-byte units
Bits 30-29
MLFLP (ML-layer Flip mode) Set flipping mode for Middle Left (ML) layer 00 01 10 11 Display frame 0 Display frame 1 Switch frame 0 and 1 back and forth Reserved
Bit 31
MLC (ML-layer Color mode) Sets color mode for Middle Left (ML) layer 0 1 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel)
108
MLOA0 (ML-layer Origin Address 0)
Register address Bit # DisplayBaseAddress + 44h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care MLOA0 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame0) of the Middle Left (ML) layer. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. MLDA0 (ML-layer Display Address 0)
Register address Bit # DisplayBaseAddress + 48h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 MLDA0 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Middle Left (ML) layer display field in frame0. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. MLOA1 (ML-layer Origin Address 1)
Register address Bit # DisplayBaseAddress + 4Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care MLOA1 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame1) of the Middle Left (ML) layer. Since the lowest 4-bits are fixed to 0, this address is 16-byte aligned. MLDA1 (ML-layer Display Address 1)
Register address Bit # DisplayBaseAddress + 50h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 MLDA1 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Middle Left (ML) layer display field in frame1. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. MLDX (ML-layer Display position X)
Register address Bit # DisplayBaseAddress + 54h 15 14 13 12 11 10 9 8 7 6 MLDX RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
109
Set the display start position (X-coordinate) for the ML layer in pixel units relative to the origin of the logical frame. MLDY (ML-layer Display position Y)
Register address Bit # DisplayBaseAddress + 56h 15 14 13 12 11 10 9 8 7 6 MLDY RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
Set the display start position (Y-coordinate) for the ML layer in pixel units relative to the origin of the logical frame. MRM (MR-layer Mode)
Register address Bit # DisplayBaseAddress + 58 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MRC RW
9
8
7
6
5
4
3
2
1
0
Bit field name R/W Default
MRFLP
Reserve R0 0
MRW RW Don't care
Reserve R0 0
MRH RW Don't care
R0 0
0
Bits 11-0
MRH (MR-layer Height) Set height of Middle Right (MR) layer logical frame size in raster units. Setting + 1 is the height.
Bits 23-16
MRW (MR-layer memory Width) Set width of Middle Right (MR) layer logical frame size in 64-byte units
Bits 30-29
MRFLP (MR-layer Flip mode) Set flipping mode for Middle Right (MR) layer 00 01 10 11 Display frame 0 Display frame 1 Switch frame 0 and 1 back and forth Reserved
Bit 31
MRC (MR-layer Color mode) Sets color mode for Middle Right (MR) layer 0 1 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel)
110
MROA0 (MR-layer Origin Address 0)
Register address Bit # DisplayBaseAddress + 5Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care MROA0 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame0) of the Middle Right (MR) layer. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. MRDA0 (MR-layer Display Address 0)
Register address Bit # DisplayBaseAddress + 60h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 MRDA0 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Middle Left (ML) layer display field in frame0. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. MROA1 (MR-layer Origin Address 1)
Register address Bit # DisplayBaseAddress + 64h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care MROA1 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame1) of the Middle Right (MR) layer. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. MRDA1 (MR-layer Display Address 1)
Register address Bit # DisplayBaseAddress + 68h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 MRDA1 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Middle Right (MR) layer display field in frame1. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. MRDX (MR-layer Display position X)
Register address Bit # DisplayBaseAddress + 6Ch 15 14 13 12 11 10 9 8 7 6 MRDX RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
111
Set the display start position (X-coordinate) for the MR layer in pixel units relative to the origin of the logical frame. MRDY (MR-layer Display position Y)
Register address Bit # DisplayBaseAddress + 6Eh 15 14 13 12 11 10 9 8 7 6 MRDY RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
Set the display start position (Y-coordinate) for the MR layer in pixel units relative to the origin of the logical frame. BLM (BL-layer Mode)
Register address Bit # DisplayBaseAddress + 70h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BLC RW
9
8
7
6
5
4
3
2
1
0
Bit field name R/W Default
BLFLP R0 0
Reserve R0 0
BLW RW Don't care
Reserve R0 0
BLH RW Don't care
0
Bits 11-0
BLH (BL-layer Height) Set height of Base Left (BL) layer logical frame size in raster units. Setting + 1 is the height.
Bits 23-16
BLW (BL-layer memory Width) Set width of Base Left (BL) layer logical frame size in 64-byte units
Bits 30-29
BLFLP (BL-layer Flip mode) Set flipping mode for Base Left (BL) layer 00 01 10 11 Display frame 0 Display frame 1 Switch frame 0 and 1 back and forth Reserved
Bit 31
BLC (BL-layer Color mode) Sets color mode for Base Left (BL) layer 0 1 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel)
112
BLOA0 (BL-layer Origin Address 0)
Register address Bit # DisplayBaseAddress + 74h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care BLOA0 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame0) of the Base Left (BL) layer. Since the lowest 4 bits are fixed to 0, this address is 16byte aligned. BLDA0 (BL-layer Display Address 0)
Register address Bit # DisplayBaseAddress + 78h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 BLDA0 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Base Left (BL) layer display field in frame0. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. BLOA1 (BL-layer Origin Address 1)
Register address Bit # DisplayBaseAddress + 7Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care BLOA1 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame1) of the Base Left (BL) layer. Since the lowest 4 bits are fixed to 0, this address is 16byte aligned. BLDA1 (BL-layer Display Address 1)
Register address Bit # DisplayBaseAddress + 80h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 BLDA1 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Base Left (BL) layer display field in frame1. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. BLDX (BL-layer Display position X)
Register address Bit # DisplayBaseAddress + 84h 15 14 13 12 11 10 9 8 7 6 BLDX RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
113
Set the display start position (X-coordinate) for the BL layer in pixel units relative to the origin of the logical frame. BLDY (BL-layer Display position Y)
Register address Bit # DisplayBaseAddress + 86h 15 14 13 12 11 10 9 8 7 6 BLDY RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
Set the display start position (Y-coordinate) for the BL-layer in pixel units relative to the origin of the logical frame. BRM (BR-layer Mode)
Register address Bit # DisplayBaseAddress + 88h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BRC RW
9
8
7
6
5
4
3
2
1
0
Bit field name R/W Default
BRFLP R0 0
Reserve R0 0
BRW RW Don't care
Reserve R0 0
BRH RW Don't care
0
Bits 11-0
BRH (BR-layer Height) Set height of Base Right (BR) layer logical frame size in raster units. Setting + 1 is the height.
Bits 23-16
BRW (BR-layer memory Width) Set width of Base Right (BR) layer logical frame size in 64-byte units
Bits 30-29
BRFLP (BR-layer Flip mode) Set flipping mode for Base Right (BR) layer 00 01 10 11 Display frame 0 Display frame 1 Switch frame 0 and 1 back and forth Reserved
Bit 31
BRC (BR-layer Color mode) Sets color mode for Base Right (BR) layer 0 1 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel)
114
BROA0 (BR-layer Origin Address 0)
Register address Bit # DisplayBaseAddress + 8Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care BROA0 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame0) of the Base Right (BR) layer. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. BRDA0 (BR-layer Display Address 0)
Register address Bit # DisplayBaseAddress + 90h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 BRDA0 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the Base Right (BR) layer display field in frame0. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. BROA1 (BR-layer Origin Address 1)
Register address Bit # DisplayBaseAddress + 94h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care BROA1 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the logical frame (frame1) of the Base Right (BR) layer. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. BRDA1 (BR-layer Display Address 1)
Register address Bit # DisplayBaseAddress + 98h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 BRDA1 RW Don't care 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of Base Right (BR) layer display field in frame1. When the direct color mode is used, the LSB is fixed to 0 and this address is 2-byte aligned. BRDX (BR-layer Display position X)
Register address Bit # DisplayBaseAddress + 9Ch 15 14 13 12 11 10 9 8 7 6 BRDX RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
115
Set the display start position (X-coordinate) for the BR layer in pixel units relative to the origin of the logical frame. BRDY (BR-layer Display position Y)
Register address Bit # DisplayBaseAddress + 9Eh 15 14 13 12 11 10 9 8 7 6 BRDY RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
T Set the display start position (Y-coordinate) for the BR layer in pixel units relative to the origin of the logical frame. CUTC (CUrsor Transparent Control)
Register address Bit # DisplayBaseAddress + A0h 15 14 13 12 Reserved R0 0 11 10 9 8 CUZT RW Don't care 7 6 5 4 CUTC RW Don't care 3 2 1 0
Bit field name R/W Default
Bits 7-0
CUTC (Cursor Transparent Code) Set transparency color code
Bit 8
CUZT (Cursor Zero Transparency) Defines treatment of color code 0 0 1 Code 0 transparency color Code 0 not transparency color
116
CPM (Cursor Priority Mode)
Register address Bit # DisplayBaseAddress + A2h 7 Reserved R0 0 6 5 CEN1 RW 0 4 CEN0 RW 0 3 Reserved R0 0 2 1 CUO1 RW 0 0 CUO0 RW 0
Bit field name R/W Default
This register controls the display priority of cursors. Cursor 0 is always prioritized to cursor 1.
Bit 0 CUO0 (Cursor Overlap 0) Sets display priority between cursor 0 and pixels of Console layer 0 1 Put cursor 0 at bottom of Console layer. Put cursor 0 at top of Console layer.
Bit 1
CUO1 (Cursor Overlap 1) Sets display priority between cursor 1 and pixels of Console layer 0 1 Put cursor 1 at bottom of Console layer. Put cursor 1 at top of Console layer.
Bit 4
CEN0 (Cursor Enable 0) Sets display enable of cursor 0 0 1 Disable Enable
Bit 5
CEN1 (Cursor Enable 1) Sets display enable of cursor 1 0 1 Disable Enable
CUOA0 (Cursor-0 Origin Address)
Register address Bit # DisplayBaseAddress + A4h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care CUOA0 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the start address of the cursor-0 pattern. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned.
117
CUX0 (Cursor-0 X position)
Register address Bit # DisplayBaseAddress + A8h 15 14 13 12 11 10 9 8 7 6 CUX0 RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the horizontal position of the cursor-0 pattern left edge. Set the left-edge position of the cursor-0 pattern from the start edge of the display field in dot-clock units. CUY0 (Cursor-0 Y position)
Register address Bit # DisplayBaseAddress + Aah 15 14 13 12 11 10 9 8 7 6 CUY0 RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the vertical position of the cursor-0 pattern top edge. Set the top edge position of the cursor-0 pattern from the start edge of the display field in raster units. CUOA1 (Cursor-1 Origin Address)
Register address Bit # DisplayBaseAddress + ACh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care CUOA1 R0 0000 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the start address of the cursor-1 pattern. Since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. CUX1 (Cursor-1 X position)
Register address Bit # DisplayBaseAddress + B0h 15 14 13 12 11 10 9 8 7 6 CUX1 RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the horizontal position of the cursor-1 pattern left edge. Set the left edge position of the cursor-0 pattern from the start edge of the display field in dot-clock units.
118
CUY1 (Cursor-1 Y position)
Register address Bit # DisplayBaseAddress + B2h 15 14 13 12 11 10 9 8 7 6 CUY1 RW Don't care 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
This register controls the vertical position of the cursor-1 pattern top edge. Set the top edge position of the cursor-0 pattern from the start edge of the display field in raster units. BRATIO (Blend Ratio)
Register address Bit # DisplayBaseAddress + B4h 15 BRS RW 0 14 13 12 11 Reserved R0 0 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
BRATIO RW 0
Reserved R0 0000
This register controls the blending ratio for Console layer pixels when using the blending mode.
Bits 7-4 BRATIO (Blend Ratio) Set blending ratio 0000 0001 : 1111 Coefficient = 0 Coefficient = 1/16 : Coefficient = 15/16
Bit 15
BRS (Blend Ratio Select) Selects formula for alpha blending 0 1 (C-layer color x Coefficient) + (Combination color of W/M/B layers x (1 - Coefficient)) (C-layer color x (1 - Coefficient)) + (Combination color of W/M/B layers x Coefficient)
BMODE (Blend MODE)
Register address Bit # DisplayBaseAddress + B6h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
Reserved R0 0
Reserve BLEND
R0 0
RW 0
This register controls the Console layer overlay options. The color set as a transparent color is irrelevant to the alpha bit and blend processing is not performed.
Bit 0 BLEND Overlays mode between C and B/M/W 0 1 Simple priority mode (C-layer given priority at all times) Blending mode
119
When performing blend processing, specify the blend mode for this bit; alpha must be enabled previously in C-layer display data. In the direct color mode, specify alpha for the most significant bit. In the indirect color mode, specify alpha for the most significant bit of pallet data. KEYC (Key Color)
Register address Bit # DisplayBaseAddress + B8h 15 KYEN RW 0 14 13 12 11 10 9 8 7 KYC RW Don't care 6 5 4 3 2 1 0
Bit field name R/W Default
Bits 14-0
KYC (Key Color) Set key color for chroma-key operation. Bits 7-0 used in indirect color mode. Bits 7-0 are used when the indirect color mode (8 bits/pixel) and the chroma key mode are set to the C-layer color.
Bit 15
KYEN (chroma-Key Enable) Enables/disables chroma-key operation 0 1 Disable chroma-key operation (H always output from GV pin). Enable chroma-key operation.
CKM (Chroma Key Mode)
Register address Bit # DisplayBaseAddress + BAh 15 14 13 12 11 10 9 8 Reserved R0 0 7 6 5 4 3 2 1 0 KCS RW 0
Bit field name R/W Default
Bit 0
KCS (Key Color Select) Selects key color as C-layer color or display color 0 1 Set key color as display color. Set key color as C-layer color.
(See Sect i on 5.5.)
120
CTC (C-layer Transparent Control)
Register address Bit # DisplayBaseAddress + BCh 15 CZT RW 0 14 13 12 11 10 9 8 7 CTC RW Don't care 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the transparent color setting for the C layer. The color defined as a transparent color by this register is treated as a transparent color even in the blending mode. When both CTC and CZT are set to 0, color 0 is displayed in black (not transparent).
Bits 14-0 CTC (C-layer Transparent Color) Set color code of transparent color used in Console layer. Bits 7-0 used in indirect color mode.
Bit 15
CZT (C-layer Zero Transparency) Sets treatment for code 0 in Console layer 0 1 Code 0 not transparent color Code 0 transparent color
MRTC (MR-layer Transparent Control)
Register address Bit # DisplayBaseAddress + C0h 15 MRZT RW 0 14 13 12 11 10 9 8 7 MRTC RW Don't care 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the transparent color setting for the MR-layer. When both MRTC and MRZT are set to 0, color 0 is displayed in black (not transparent).
Bits 14-0 MRTC (MR-layer Transparent Color) Set color code of transparent color used in MR-layer. Bits 7-0 used in indirect color mode.
Bit 15
MRZT (MR-layer Zero Transparency) Sets treatment for code 0 in MR-layer 0 1 Code 0 not transparent color Code 0 transparent color
121
MLTC (ML-layer Transparent Control)
Register address Bit # DisplayBaseAddress + C2h 15 MLZT RW 0 14 13 12 11 10 9 8 7 MLTC RW Don't care 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the transparent color setting for the ML-layer. When both MLTC and MLZT are set to 0, color 0 is displayed in black (not transparent).
Bits 14-0 MLTC (ML-layer Transparent Color) Set color code of transparent color used in ML-layer. Bits 7-0 used in indirect color mode.
Bit 15
MLZT (ML-layer Zero Transparency) Sets treatment for code 0 in ML-layer 0 1 Code 0 not transparent color Code 0 transparent color
CPAL0-255 (C-layer Pallet 0-255)
Register address Bit # DisplayBaseAddress + 400h -- DisplayBaseAddress + 7FFh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 A
RW
Don' t care
8
7
6
5
4 B
3
2
1
0
Bit field name R/W Default
R RW Don't care R0 00 RW
G R0 00 RW
R0 0000000
R0 00
Don't care
Don't care
These are color pallet registers for Console layer and cursors. In the indirect color mode, a color code in the display field indicates the pallet register number (pallet entry number), and the color information set in that entry is applied as the display color of that pixel.
Bits 7-2 B (Blue) Set blue color element
Bit 15-10
G (Green) Set green color element
Bits 23-18
R (Red) Set red color element
Bit 31
A (Alpha) When blending mode used, color blended with B/M/W layer pixel color according to blending ratio for pixel of C layer with bit = 1. Alpha blending mode ignored when used as cursor color.
122
MBPAL0-255 (M-layer and B-layer Pallet 0-255)
Register address Bit # DisplayBaseAddress + 800h -- DisplayBaseAddress + BFFh 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserve R0 0 RW Don't care R R0 00 RW Don't care G R0 00 RW Don't care 8 7 6 5 4 B R0 00 3 2 1 0
Bit field name R/W Default
These are color pallet registers for Middle and Base layers. In the indirect color mode, a color code in the display field indicates the pallet register number (pallet entry number), and the color information set in that entry is applied as the display color of that pixel.
Bits 7-2 B (Blue) Set blue color element
Bits 15-10
G (Green) Set green color element
Bits 23-18
R (Red) Set red color element
123
7.1.4 Draw Control Registers
CTR (Control Register)
Register address Bit # DrawBaseAddress + 400h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FO PE CE
RW RW RW
8
7
6
5
4
3
2
1 PS R 00
0
Bit field name R/W Default
FCNT R 100000
NF FF FE R 0 R 0 R 1
SS R 00
DS R 00
0
0
0
This register indicates draw flags and status. Bits 24-22 are not cleared until 0 is set.
Bits 1-0 PS (Pixel engine Status ) Indicate status of pixel engine unit 00 01 10 11 Idle Busy Reserved Reserved
Bits 5-4
DS (DDA Status) Indicate status of DDA 00 01 10 11 Idle Busy Reserved Reserved
Bits 9-8
SS (Setup Status) Indicate status of Set up unit 00 01 10 11 Idle Busy Reserved Reserved
Bit 12
FE (FIFO Empty) Indicates status of display list FIFO 0 1 Valid data No valid data
Bit 13
FF (FIFO Full) Indicates fullness of display list FIFO 0 1 Not full Full
Bit 14
NF (FIFO Near Full) Indicates entries of display list FIFO 0 Empty entries equal to or more than half
124
1
Empty entries less than half
Bits 20-15
FCNT(FIFO Counter) Indicate number of empty entries (0: Full - 32: Empty)
Bit 22
CE (Display List Command Error) Indicates command error detection 0 1 Normal Command error detected
Bit 23
PE (Display List Packet code Error) Indicates packet code error detection 0 1 Normal Packet code error detected
Bit 24
FO (FIFO Overflow) Indicates FIFO overflow status 0 1 Normal FIFO overflow detected
IFSR (Input FIFO Status Register)
Register address Bit # DrawBaseAddress + 404h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
NF FF FE R 0 R 0 R 1
This is a miller register for bits 14-12 of the CTR register. IFCNT (Input FIFO Counter)
Register address Bit # DrawBaseAddress + 408h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
FCNT R 100000
This is a miller register for bits 19-15 of the CTR register. SST (Setup engine Status)
Register address Bit # DrawBaseAddress + 40Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SS R 00 0
Bit field name R/W Default
This is a miller register for bits 9-8 of the CTR register.
125
DST (DDA Status)
Register address Bit # DrawBaseAddress + 410h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
DS RW 00
This is a miller register for bits 5-4 of the CTR register. PST (Pixel engine Status)
Register address Bit # DrawBaseAddress + 414h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PS RW 00 0
Bit field name R/W Default
This is a miller register for bits 1-0 of the CTR register. EST (Error Status)
Register address Bit # DrawBaseAddress + 418h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
FO PE CE
RW RW RW
0
0
0
This is a miller register for bits 24-22 of the CTR register.
126
7.1.5 Draw mode Parameter Registers
When wirte to the registers, use the SetRegister command. The registers cannot be accessed from the CPU. MDR0 (Mode Register for miscellaneous)
Register address Bit # DrawBaseAddress + 420h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CF
RW
9
8
7
6
5
4
3
2
1
0
Bit field name R/W Default
CY CX
RW RW
BSV RW 00
BSH RW 00
0
0
0
Bits 1-0
BSH (Bitmap Scale Horizontal) Set horizontal zoom ratio of bitmap draw 00 01 10 01 x1 x2 x1/2 Reserved
Bits 3-2
BSV (Bitmap Scale Vertical) Set vertical zoom ratio of bitmap draw 00 01 10 01 x1 x2 x1/2 Reserved
Bit 8
CX (Clip X enable) Sets X-coordinate clipping mode 0 1 Disable Enable
Bit 9
CY (Clip Y enable) Sets Y-coordinate clipping mode 0 1 Disable Enable
Bit 15
CF (Color Format) Sets drawing color format of current draw frame 0 1 Indirect color mode (8 bits/pixel) Direct color mode (16 bits/pixel)
127
MDR1 (Mode Register for LINE)
DrawBaseAddress + 424h Register address 31 Bit # 30 29 28 27 26 25 24 23 22 LW RW 00000 21 20 19 18 17 16 15 14 13 12 11 10 BL
RW
9
8
7
6 ZW
RW
5
4 ZCL RW 0000
3
2 ZC
RW
1
0
Bit field name R/W Default
LOG RW 0011
BM RW 0
0
0
0
This register controls the mode of line draw and pixel plot.
Bit 2 ZC (Z Compare mode) Sets Z comparison mode 0 1 Disable Enable
Bits 5-3
ZCL (Z Compare Logic) Select type of Z comparison 000 001 010 011 100 101 110 111 NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL
Bit 6
ZW (Z Write mask) Sets ZWRITEMASK 0 1 Compare Z values and overwrite result to Z buffer. Compare Z values and do not overwrite to Z buffer.
Bits 8-7
BM (Blend Mode) Set blend mode 00 01 10 11 Normal (source copy) Alpha blending Logical calculation enable Reserved
128
Bits 12-9
LOG (Logical operation) Set type of logical calculation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLEAR AND AND REVERSE COPY AND INVERTED NOP XOR OR NOR EQUIV INVERT OR REVERSE COPY INVERTED OR INVERTED NAND SET
Bit 19
BL (Broken Line) Selects line type 0 1 Solid line Broken line
Bits 28-24
LW (Line Width) Set line width 00000 00001 : 11111 1 pixel 2 pixels : 32 pixels
129
MDR2 (Mode Register for Polygon)
DrawBaseAddress + 428h Register address 31 Bit # 30 29 28 27 26 25 24 23 22 TT RW 00 21 20 19 18 17 16 15 14 13 12 11 10 LOG RW 0011 9 8 7 6 ZW
RW
5
4 ZCL RW 0000
3
2 ZC
RW
1
0 SM
RW
Bit field name R/W Default
BM RW 0
0
0
0
This register controls the polygon draw mode.
Bit 0 SM (Shading Mode) Sets shading mode 0 1 Flat shading Gouraud shading
Bit 2
ZC (Z Compare mode) Sets Z comparison mode 0 1 Disable Enable
Bits 5-3
ZCL (Z Compare Logic) Select type of Z comparison 000 001 010 011 100 101 110 111 NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL
Bit 6
ZW (Z Write mask) Sets ZWRITEMASK 0 1 Compare Z values and overwrite result to Z buffer Compare Z values and do not overwrite result to Z buffer
Bits 8-7
BM (Blend Mode) Set blend mode 00 01 10 11 Normal (source copy) Alpha blending Logical calculation enable Reserved
130
Bits 12-9
LOG (Logical operation) Set type of logical calculation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLEAR AND AND REVERSE COPY AND INVERTED NOP XOR OR NOR EQUIV INVERT OR REVERSE COPY INVERTED OR INVERTED NAND SET
Bits 29-28
TT (Texture-Tile Select) Select texture or tile pattern 00 01 10 11 Not used Enable tiling operation Enable texture mapping Reserved
131
MDR3 (Mode Register for Texture)
DrawBaseAddress + 42Ch Register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit # 15 14 13 12 11 10 9 TWS RW 00 8 7 6 5
TF RW
4
3
TC RW
2
1
0
TBU
Bit field name R/W Default
TAB RW 00
TBL RW 00
TWT RW 00
RW
0
0
0
This register controls the texture mapping mode.
Bit 0 TBU (Texture Buffer) Selects texture memory (internal buffer always used in tiling) 0 External Graphics Memory 1 Internal texture buffer TC (Texture coordinates Correct) Controls perspective correction mode 0 Disable 1 Enable TF (Texture Filtering) Sets texture filtering mode 0 Point sampling 1 Bi-linear filtering TWT (Texture Wrap T) Set texture T-coordinate wrapping mode 00 Repeat 01 Cramp 10 Border 11 Reserved TWS (Texture Wrap S) Set texture S coordinate wrapping mode 00 Repeat 01 Cramp 10 Border 11 Reserved TBL (Texture Blend mode) Set texture blending mode 00 Decal 01 Modulate 10 Stencil 11 Reserved TAB (Texture Alpha Blend mode) Set texture alpha blending mode. The stencil alpha mode is used only when the BM bits in the MDR1 register are set to 01 (alpha blending). If any other mode is set at the BM bit field, the stencil alpha mode is treated as the stencil mode. 00 Normal 01 Stencil 10 Stencil alpha 11 Reserved
Bit 3
Bit 5
Bits 9-8
Bits 11-10
Bits 17-16
Bits 21-20
132
MDR4 (Mode Register for BLT)
Register address Bit # DrawBaseAddress + 430h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LOG RW 0011 8 7 6 5 4 3 2 1 0 TI
RW
Bit field name R/W Default
BM RW 00
0
This register controls the BitBLT. Mode.
Bits 8-7 BM (Blend Mode) Set blend mode 00 01 10 11 Normal (source copy) Reserved Logical calculation enable Reserved
Bits 12-9
LOG (Logical operation) Set logical calculation type 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLEAR AND AND REVERSE COPY AND INVERTED NOP XOR OR NOR Reserved INVERT OR REVERSE COPY INVERTED OR INVERTED NAND SET
133
FBR (Frame buffer Base)
Register address Bit # DrawBaseAddress + 440h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 FBASE RW Don't care R0 0 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the base address of the drawing frame memory. XRES (X Resolution)
Register address Bit # DrawBaseAddress + 444h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
XRES RW Don't care
This register controls the drawing frame horizontal resolution. ZBR (Z-buffer Base)
Register address Bit # DrawBaseAddress + 448h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ZBASE RW Don't care R0 0 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the Z-buffer base address. TBR (Texture memory Base)
Register address Bit # DrawBaseAddress + 44Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TBASE RW Don't care R0 0 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the texture memory base address. PFBR (2D Polygon Flag-Buffer Base)
Register address Bit # DrawBaseAddress + 450h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PFBASE RW Don't care R0 0 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the polygon flag buffer base address.
134
CXMIN (Clip X minimum)
Register address Bit # DrawBaseAddress + 454h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
CLIPXMIN RW Don't care
This register controls the clip frame minimum X position. CXMAX (Clip X maximum)
Register address Bit # DrawBaseAddress + 458h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
CLIPXMAX RW Don't care
This register controls the clip frame maximum X position. CYMIN (Clip Y minimum)
Register address Bit # DrawBaseAddress + 45Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
CLIPYMIN RW Don't care
This register controls the clip frame minimum Y position. CYMAX (Clip Y maximum)
Register address Bit # DrawBaseAddress + 460h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
CLIPYMAX RW Don't care
This register controls the clip frame maximum Y position.
135
TXS (Texture Size)
Register address Bit # DrawBaseAddress + 464h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TXSN RW 100000000 8 7 6 5 4 TXSM RW 100000000 3 2 1 0
Bit field name R/W Default
This register controls the texture size (m, n).
Bits 8-0 TXSM (Texture Size M) Set horizontal texture size. Any power of 2 between 4 and 256 can be used. Values that are not a power of 2 cannot be used. 000000100 000001000 000010000 000100000 001000000 010000000 100000000 Others M=4 M=8 M=16 M=32 M=64 M=128 M=256 Prohibited
Bits 24-16
TXSN (Texture Size N) Set vertical texture size. Any power of 2 between 4 and 256 can be used. Values that are not a power of 2 cannot be used. 000000100 000001000 000010000 000100000 001000000 010000000 100000000 Others N=4 N=8 N=16 N=32 N=64 N=128 N=256 Prohibited
136
TIS (Tile Size)
Register address Bit # DrawBaseAddress + 468h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TISN RW 1000000 8 7 6 5 4 3 TISM RW 1000000 2 1 0
Bit field name R/W Default
This register controls the tile size (m, n).
Bits 6-0 TISM (Title Size M) Set horizontal tile pattern size. Any power of 2 between 4 and 64 can be used. Values that are not a power of 2 cannot be used. 0.000100 0001000 0010000 0100000 1000000 Others M=4 M=8 M=16 M=32 M=64 Prohibited
Bits 22-16
TISN (Title Size N) Set vertical tile pattern size. Any power of 2 between 4 and 643 can be used. Values that are not a power of 2 cannot be used. 0000100 0001000 0010000 0100000 1000000 Others N=4 N=8 N=16 N=32 N=64 Prohibited
TOA (Texture Buffer Offset address)
Register address Bit # DrawBaseAddress + 46Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
XBO RW Don't care
This register controls the texture buffer offset address of. By using this offset value, multiple texture patterns can be used and referred to the texture buffer memory. Specify the word-aligned byte address (16 bits). (Bit 0 is always 0.)
137
FC (Foreground Color)
Register address Bit # DrawBaseAddress + 480h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
FGC RW 0
This register controls the drawing frame foreground color. This color is used for the object color of flat shading and foreground color of bitmap draw and broken line draw. At bitmap drawing, all bits set to 1 are drawn in the color set at this register.
Bits 15-0 FGC (Foreground Color) Set foreground color value. In the indirect color mode, the lower 8 bits (bits 7-0) are used.
BC (Background Color)
Register address Bit # DrawBaseAddress + 484h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BT
RW
8
7 BGC RW 0
6
5
4
3
2
1
0
Bit field name R/W Default
0
This register controls the drawing frame background color. This color is used for the background color of bitmap draw and broken line draw. At bitmap drawing, all bits set to 1 are drawn in the color set at this register.
Bits 14-0 BGC (Background Color) Set background color value. In the indirect color mode, the lower 8 bits (bit 7-0) are used.
Bit 15
BT (Background Transparency) Sets transparent mode of background color 0 1 Draw background in color used in BGC field. Don't draw background (use current color).
138
ALF (Alpha Factor)
Register address Bit # DrawBaseAddress + 488h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 A RW 0 3 2 1 0
Bit field name R/W Default
This register controls the alpha blending ratio. BLP (Broken Line Pattern)
Register address Bit # DrawBaseAddress + 48Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BLP RW 0 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the broken-line pattern. The bit 1 set in the brokenline pattern is drawn in the foreground color and bit 0 is drawn in the background color. The actual line pattern is pasted from MSB to LSB to the line to be drawn. If the length of the applied line is longer than 32 bits, the same line pattern is wrapped around in 32-bit units. The current position (bit #) of the line pattern used for the line is set in the BLPO register. TBC (Texture Border Color)
Register address Bit # DrawBaseAddress + 494h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 R0 0 8 7 BC RW 0 6 5 4 3 2 1 0
Bit field name R/W Default
This register controls the texture mapping border color.
Bits 14-0 BC (Border Color) Set border color of texture mapping. Only the direct color mode is used.
139
BLPO (Broken Line Pattern Offset)
Register address Bit # DrawBaseAddress + 3E0h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 BCR RW 11111 1 0
Bit field name R/W Default
This register controls the start bit position of the broken line pattern set to BLP registers, for broken line drawing. The lowest 5 bits contain the bit number of the broken line pattern. This value is decremented at each pixel draw. Broken line drawing can be started from any position of the specified broken line pattern by setting any number at this register.
140
7.1.6 Triangle Draw Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command. (XY-coordinate register)
Register Ys Xs dXdy XUs dXUdy XLs dXLdy USN LSN Address 0000h 0004h 0008h 000ch 0010h 0014h 0018h 001bh 0020h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 S S S S S S S 0 0 S S S S S S S 0 0 S S S S S S S 0 0 S S S S S S S 0 0 Int Int Int Int Int Int Int Int Int 9 8 0 Frac Frac Frac Frac Frac Frac 0 0 7 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets (X, Y) coordinates for triangle drawing
Ys Xs dXdy XUs dXUdy XLs dXLdy USN LSN Y-coordinate start position of long side X-coordinate start position of long side X DDA value of long side X-coordinate start position of top side X DDA value of top side X-coordinate start position of bottom side X DDA value of lower side Number of spans (rasters) of top triangle. If this value is 0, the top triangle is not drawn. Number of spans (rasters) of bottom triangle. If this value is 0, the bottom triangle is not drawn.
(Color register)
Register Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy Address 0040h 0044h 0048h 004Ch 0050h 0054h 0058h 005ch 0060h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S 0 S S Int Int Int Int Int Int Int Int Int 9 8 7 6 5 4 3 2 1 0 Frac Frac Frac Frac Frac Frac Frac Frac Frac
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
141
Sets color parameters for triangle drawing. These parameters are used in the Gouraud shading mode.
Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy R value at (Xs, Ys, Zs) of long side R DDA value of horizontal way R DDA value of long side G value at (Xs, Ys, Zs) of long side G DDA value of horizontal way G DDA value of long side B value at (Xs, Ys, Zs) of long side B DDA value of horizontal way B DDA value of long side
(Z-coordinate register)
Register Zs dZdx dZdy Address 0080h 0084h 008ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 S S Int Int Int 9 8 7 Frac Frac Frac 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets Z-coordinate for 3D triangle drawing
Zs dZdx dZdy Z-coordinate start position of long side Z DDA value of horizontal way Z DDA value of long side
(Texture coordinate register)
Register Ss dSdx dSdy Ts dTdx dTdy Qs dQdx dQdy Address 00c0h 00c4h 00c8h 00cch 00d0h 00d4h 00d8h 00dch 00e0h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 S S S S S S 0 S S S S S S S S 0 S S S S S S S S 0 S S S S S S S S 0 S S S S S S S S 0 S S S S S S S S 0 S S S S S S S S 0 Int S Int S Int Int Int Int Int Int Int Frac Frac Frac 9 8 7 6 5 4 3 2 1 0 Frac Frac Frac Frac Frac Frac
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
142
Sets texture coordinate parameters for triangle drawing
Ss dSdx dSdy Ts dTdx dTdy Qs dQdx dQdy S-coordinate of texture at (Xs, Ys, Zs) of long side S DDA value of horizontal way S DDA value of long side T-coordinate of texture at (Xs, Ys, Zs) of long side T DDA value of horizontal way T DDA value of long side Q (Perspective correction value) of texture at (Xs, Ys, Zs) of long side Q DDA value of horizontal way Q DDA value of long side
143
7.1.7 Line Draw Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command. (Coordinate register)
Register LPN LXs LXde LYs LYde LZs LZde Address 0140h 0144h 0148h 014ch 0150h 0154h 0158h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 S S S S S S 0 S S S S 0 S S S S 0 S S S S S S S S S Int Int S S S S S Int Int S S S S S S S S S S S Int S Int Int 9 8 0 Frac Frac Frac Frac Frac Frac 7 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets coordinate parameters for line drawing
LPN LXs Pixel length of line (*1) X-coordinate position of line draw start vertex (-Pai/4 Line angle Pai/4) Set truncated integer value of X-coordinate. (Other than above) Set current integer part of fixed point X-coordinate data. LXde Line angle data for X axis (-Pai/4 /LQH DQJOH Pai/4) Increment or decrement according to drawing direction. (Other than above) Set fraction part of DX/DY. Y-coordinate position of line Pai draw start vertex (-Pai/4 Line angle Pai/4) Set current integer part of fixed point Y-coordinate data. (Other than above) Set truncated integer value of Y-coordinate. LYde Line angle data for Y-axis (-Pai/4 Line angle Pai/4) Set fraction part of dY/dX. (Other than above) Increment or decrement according to drawing direction. Z-coordinate position of line draw start vertex Z angle
LYs
LZs LZde
(*1)
If -Pai/4 Line angle Pai/4: Horizontal length of line in pixel units Other than above: Vertical length of line in pixel units
144
(Color register)
Register LRs LRde LGs LGde LBs LBde Address 015ch 0160h 0164h 0168h 016ch 0170h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S Int Int Int Int Int Int 8 7 6 5 4 3 2 1 0 Frac Frac Frac Frac Frac Frac
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets color parameters for line drawing. These parameters are used in the Gouraud shading mode.
LRs LRde LGs LGde LBs LBde R value at line draw start vertex Differential value of R element G value at line draw start vertex Differential value of G element B value at line draw start vertex Differential value of B element
7.1.8 Pixel Plot Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command.
Register PXdc PYdc PZdc Address 0180h 0184h 0188h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 0 0 0 0 Int Int Int 8 0 0 0 7 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets coordinate parameter for pixel plot. The foreground color is used.
PXdc PYdc PZdc
Set X-coordinate position Set Y-coordinate position Set Z-coordinate position
145
7.1.9 Rectangle Draw Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command.
Register RXs RYs RsizeX RsizeY
Address 0200h 0204h 0208h 020ch
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int Int Int Int
9
8 0 0 0 0
7
6
5
4
3
2
1
0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets coordinate parameters for rectangle drawing. The foreground color is used.
RXs RYs RsizeX RsizeY
Set the X-coordinate of top left vertex Set the Y-coordinate of top left vertex Set horizontal size Set vertical size
146
7.1.10 Blt Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command.
Register SADDR SStride SRXs SRYs DADDR DStride DRXs DRYs BRsizeX BRsizeY Address 0240h 0244h 0248h 024ch 0250h 0254h 0258h 025ch 0260h 0264h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int Int Int Int Int 0 0 0 Int Int Int Address 0 0 0 0 0 Address 0 0 0 9 8 7 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets parameters for Blt operations
SADDR SStride SRXs SRYs DADDR DStride DRXs DRYs BRsizeX BRsizeY Sets start address of source field in byte boundary. Sets horizontal size of source field Sets start X-coordinate position of source rectangle Sets start Y-coordinate position of source rectangle Sets start address of destination rectangle in byte boundary Sets horizontal size of destination field Sets start X-coordinate position of destination rectangle Sets start Y-coordinate position of destination rectangle Sets horizontal size of rectangle Sets vertical size of rectangle
147
7.1.11 Fast2DLine Draw Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command.
Register LX0dc LY0dc LX1dc LY1dc Address 0540h 0544h 0548h 054ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int Int Int Int 9 8 0 0 0 0 7 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets coordinate parameters of both end points for Fast2DLine drawing
LX0dc LY0dc LX1dc LY1dc Sets X-coordinate of vertex V0 Sets Y-coordinate of vertex V0 Sets X-coordinate of vertex V1 Sets Y-coordinate of vertex V1
148
7.1.12 Fast2DTriangle Draw Registers
Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command.
Register X0dc Y0dc X1dc Y1dc X2dc Y2dc Address 0580h 0584h 0588h 058ch 0590h 0594h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Int Int Int Int Int Int 9 8 0 0 0 0 0 0 7 6 5 4 3 2 1 0
Address S 0 Int Frac
Offset from DrawBaseAddress
Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data
Sets coordinate parameters of three vertices for Fast2DTriangle drawing
X0dc Y0dc X1dc Y1dc X2dc Y2dc Sets X-coordinate of vertex V0 Sets Y-coordinate of vertex V0 Sets X-coordinate of vertex V1 Sets Y-coordinate of vertex V1 Sets X-coordinate of vertex V2 Sets Y-coordinate of vertex V2
7.1.12 DisplayList FIFO Registers
DFIFO (Displaylist FIFO)
Register address Bit # DrawBaseAddress + 4A0h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DFIFO W Don't care 9 8 7 6 5 4 3 2 1 0
Bit field name R/W Default
FIFO registers for DisplayList transfer
149
8 Timing Diagram
8.1 Host Interface
8.1.1 CPU Read/Write Timing Diagram for SH3 Mode 7 T1
%&/., $> @
CS
7ZK Twh1
7ZK Twh2
7 T2
%6
At read
5' '> @ : (> @ '> @ : $, 7 +L = : DL W : DL W 1RW DL :W : DL W 9DOG 'DW L D +L = 9DOG 'DW L D
At write
{:
T1: Twh*: T2:
XWAIT sampling in SH3 mode
Read/write start cycle (RDY in wait state) Cycles inserted by hardware (RDY cancels the wait state as soon as the preparations are made.) Read/write end cycle (RDY ends in the wait state.)
Fig. 8.1 CPU Read/Write Timing Diagram for SH3 Mode
150
8.1.2 CPU Read/Write Timing Diagram for SH4 Mode
T1
BCLKI A[24:2] CS BS RD D[31:0] XWE[3:0] D[31:0] RDY Hi-Z
Twh1 Twh1
Twh2 Twh2
T2
At read
Valid Data
At write
Valid Data
+L =
NotReady NotReady Ready NotReady
{:
T1: Twh*: T2:
RDY sampling in SH4 mode
Read/write start cycle (RDY is in the not-ready state.) Cycles inserted by hardware (RDY asserts Ready as soon as the preparations are made.) Read/write end cycle (RDY ends in the not-ready state.)
Fig. 8.2 CPU Read/Write Timing Diagram for SH4 Mode
151
8.1.3 CPU Read/Write Timing Diagram in V832 Mode
T1
BCYST A[23:2] CS BS MRD(IORD D[31:0] MWR(IOWR) At write xxBEN[3:0] D[31:0] READY Hi-Z
Twh1
Twh2
T2
At read
Valid Data
Valid Data Hi-Z Not-ready Not-ready Ready Not-ready Ready
{:
T1: Twh*:
READY sampling in V832 mode
Read/write start cycle (READY is in the not-ready state.) Cycles inserted by hardware (READY asserts Ready as soon as the preparations are made.) T2: Read/write end cycle (READY is in the not-ready state.) READY is placed in the ready state and then set to Hi-Z. Note: The xxBEN signal is used only when performing a write from the CPU; it is not used when performing a read from the CPU.
Fig. 8.3 CPU Read/Write Timing Diagram in V832 Mode
152
8.1.4 SH4 Single-address DMA Write (Transfer of 1 Long Word)
BCLKIN D[31:0] DREQ DRACK DTACK Bus cycle CPU DMAC *1 DMAC CPU *1 Acceptance Acceptance Acceptance
{:
*1:
DREQ sampling and channel priority determination for SH mode (DREQ = level detection) In the cycle steal mode, even when DREQ is already asserted at the 2nd DREQ sampling, the right to use the bus is returned to the CPU once. In the burst mode, DMAC secures the right to use the bus unless DREQ is negated.
Fig. 8.4 SH4 Single-address DMA Write (Transfer of 1 Long Word)
The MB86290A writes data according to the DTACK assert timing. When data cannot be received, the DREQ signal is automatically negated. And then the DREQ signal is reasserted as soon as data becomes ready to be received.
153
8.1.5 SH4 Single-address DMA Write (Transfer of 8 Long Words)
BCLKIN D[31:0] DREQ DRACK DTACK Bus cycle CPU 1st DMAC CPU *1 Acceptance Acceptance
{:
*1:
DREQ sampling and channel priority determination for SH mode (DREQ = level detection) In the cycle steal mode, even when DREQ is already asserted at the 2nd DREQ sampling, the right to use the bus is returned to the CPU once. In the burst mode, DMAC secures the right to use the bus unless DREQ is negated.
Fig. 8.5 SH4 Single-address DMA Write (Transfer of 8 Long Words)
The MB86290A writes data in accordance with the DTACK assert timing. When data cannot be received, the DREQ signal is negated automatically. And then the DREQ signal is reasserted as soon as data becomes ready to be received.
154
8.1.6 SH3/4 Dual-address DMA (Transfer of 1 Long Word)
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DREQ
Source address A[24:2] Read D[31:0]
Destination address
Source address
Destination address
Write
Read
Write
Fig. 8.6 SH3/4 Dual-address DMA (Transfer of 1 Long Word)
In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, to negate the DREQ signal when the MB86290A cannot return the Ready signal immediately, set the DBM register.
155
8.1.7 SH3/4 Dual-Address DMA (Transfer of 8 Long Words)
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DREQ
Source address A[24:2] Read 1 D[31:0] Read 2 *c*c *c * c * c Read 8 *c *c*c *c
Destination address *ccc ** Write 1 Write 2 * c c c Write 8 ** *ccc **
Fig. 8.7 SH3/4 Dual-address DMA (Transfer of 8 Long Words)
In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, to negate the DREQ signal when the MB86290A cannot return the Ready signal immediately, set the DBM register.
156
8.1.8 V832 DMA Transfer
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DMARQ
DMAAK
Source address A[23:2] Read D[31:0]
Destination address
Source address
Destination address
Write
Read
Write
Fig. 8.8 V832 DMA Transfer
During DMA transfer, the DREQ signal is kept asserted until the transfer ends by default. Consequently, to negate the DREQ signal when the MB86290A cannot return the Ready signal immediately, set the DBM register.
157
8.1.9 SH4 Single-address DMA Transfer End Timing
BCLKIN D[31:0] DREQ DRACK DTACK Last data Acceptance Acceptance
{:
DREQ sampling and channel priority determination for SH mode (DREQ = level detection) Fig. 8.9 SH4 Single-address DMA Transfer End Timing
DREQ is negated three cycles after DRACK is written as the last data.
158
8.1.10 SH3/4 Dual-address DMA Transfer End Timing
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DREQ
DRACK Source address A[24:2] Read D[31:0] Write Destination address
DTACK
Fig. 8.10 SH3/4 Dual-address DMA Transfer End Timing
DREQ is negated three cycles after DRACK is written as the last data.
159
8.1.11 V832 DMA Transfer End Timing
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DMARQ Source address A[24:2] Write Destination address
Read D[31:0]
DMAAK
XTC
Fig. 8.11 V832 DMA Transfer End Timing
DMMAK and XTC are ANDed inside the MB86290A to end DMA.
160
8.2 Graphics Memory Interface
The access timing for the MB86290A and the graphics memory is explained.
8.2.1 Timing of Read Access to Same Row Address
MCLKO
MRAS
TRCD
MCAS
MWE
MA
ROW
COL
COL
COL
COL
CL
MD
DATA
DATA
DATA
DATA
DQM
ROW: Row Address COL: Column Address DATA: READ DATA
TRCD: RAS to CAS Delay Time CL: CAS Latency
Note: This timing is used when CL2 is operating.
Fig. 8.2.1 Timing of Read Access to Same Row Address
This timing diagram shows that the same row address of SDRAM is readaccessed four times from the MB86290A. The Read command is issued after TRCD has elapsed after the ACTV command was issued. Data that is output after CL has elapsed after the Read command was issued is written to the MB86290A.
161
8.2.2 Timing of Read Access to Different Row Addresses
MCLKO
TRAS TRP
MRAS
TRCD
TRCD
MCAS
MWE
MA
ROW
COL
ROW
COL
C L
CL
MD
D ATA
DATA
DQM
ROW: Row Address COL: Column Address DATA: READ DATA
TRAS: RAS Active Time TRCD: RAS to CAS Delay Time CL: CAS Latency
TRP* RAS Precharge Time F
Note: This timing is used when CL2 is operating.
Fig. 8.2.1 Timing of Read Access to Different Row Addresses
This timing diagram shows that different row addresses of SDRAM are readaccessed from the MB86290A. An SDRAM page boundary is located between the address to be read first and the address to be read next. Consequently, the Precharge command is issued at the timing that meets the TRAS condition, and then after TRP has elapsed, the ACTV command is reissued and the Read command is issued.
162
8.2.3 Timing of Write Access to Same Row Address
MCLKO
MRAS
TRCD
MCAS
MWE
MA
ROW
COL
COL
COL
COL
MD
DATA
DATA
DATA
DATA
DQM
ROW: Row Address COL: Column Address DATA: READ DATA
TRCD: RAS to CAS Delay Time
Fig. 8.2.3 Timing of Write Access to Same Row Address
This timing diagram shows that the same row address of SDRAM is writeaccessed four times from MB86290A. The Write command is issued after TRCD has elapsed after the ACTV command is issued. Then, data is written to SDRAM.
163
8.2.4 Timing of Write Access to Different Row Addresses
MCLKO
TRAS TRP
MRAS
TRCD
TRCD
MCAS
MWE
MA
ROW
COL
ROW
COL
MD
DATA
DATA
DQM
ROW: Row Address COL: Column Address DATA: READ DATA
TRAS: RAS Active Time TRCD: RAS to CAS Delay Time TRP: RAS Precharge Time
Fig. 8.2.4 Timing of Write Access to Different Row Addresses
This timing diagram shows that different row addresses of SDRAM are writeaccessed from the MB86290A. An SDRAM page boundary is located between the address to be written to first and the address to be written to next. Consequently, the Precharge command is issued at the timing that meets the TRAS condition, and then after TRP has elapsed, the ACTV command is reissued and the Read command is issued.
164
8.2.5 Timing of Read/Write Access to Same Row Address
MCLKO
MRAS
TRCD MCAS
MWE
MA
ROW
COL
COL
CL MD DATA
LOWD DATA
DQM
ROW: Row Address COL: Column Address DATA: READ DATA
TRAS: RAS Active Time TRCD: RAS to CAS Delay Time CL: CAS Latency
TRP: RAS Precharge Time LOWD: Last Output to Write Command Delay
Note: This timing is used when CL2 is operating.
Fig. 8.2.5 Timing of Read/Write Access to Same Row Address
This timing diagram shows that a row address of SDRAM is read-accessed from the MB86290A, and then immediately afterwards the same row address is write-accessed from the MB86290A. The Write command is issued after LOWD has elapsed after read data is output from SDRAM.
165
8.2.6 Delay between ACTV Commands
MCLKO TRRD MRAS
MCAS
MWE
MA
ROW
ROW
ROW: Row Address TRRD: RAS to RAS Bank Active Delay Time
Fig. 8.2.6 Delay between ACTV Commands
The ACTV command is issued to the SDRAM row address from the MB86290A after TRRD has elapsed after the previous ACTV command is issued.
166
8.2.7 Delay between Refresh Command and Next ACTV Command
MCLKO TRC MRAS
MCAS
MWE
MA ROW: Row Address TRC: RAS Cycle Time
ROW
Fig. 8.2.7 Delay between Refresh Command and next ACTV Command
The ACTV command is issued after TRC has elapsed after the Refresh command is issued.
167
8.3 Display Timing
8.3.1 Non-interlaced Video Mode
VTR+1 rasters VSP+1 rasters VDP+1 rasters AOUTx HSYNC VSYNC Assert Frame Interrupt Assert Vsync Interrupt VSW+1 rasters
AOUTx HSYNC HDP+1 clocks HSP+1 clocks HTP+1 clocks HSW+1 clocks
In the above diagram, VTR, HDP, etc., are the settings of their associated registers.
The VSYNC/frame interrupt is asserted when display of the last raster ends. When updating display parameters, synchronize with the frame interrupt so no display disturbance occurs. Calculation for the next frame is started immediately after the vertical synchronization pulse is asserted, so the parameters must be updated by the time that calculation is started.
168
8.3.2 Interlaced Video Mode
VTR+1 rasters (odd field) VSP+1 rasters VDP+1 rasters AOUTx HSYNC VSYNC EO(out) Assert Vsync Interrupt VSW+1 rasters
AOUTx HSYNC VSYNC EO(out) VDP+1 rasters VSP+1 rasters VSW+1 rasters VTR+1 rasters (even field) Assert Frame Interrupt Assert Vsync Interrupt
In the above diagram, VTR, HDP, etc., are the settings of their associated registers.
169
Cautions
8.4 CPU Cautions
(1) Enable the hardware wait for the areas to which the MB86290A is linked. Set the software wait count to 1. (2) When starting DMA by issuing an external request, do so after setting the transfer count register (DTCR) and mode setting register (DSUR) of the MB86290A to the same value as the CPU setting. In the V832 mode, there is no need to set DTCR. (3) When MB86290A is read-/write-accessed from the CPU during DMA transfer, do not access the registers and memories related to DMA transfer. If these registers and memories are accessed, reading and writing of the correct value is not assured. (4) In the SH mode, only the lowers 32 Mbytes are used (A[25] is not used), so do not access the uppers 32 Mbytes. When linking other devices to the uppers 32 Mbytes, create Chip Select for the MB86290A by using glue logic. (5) Set DREQ (DMARQ) to detection. (6) Set the SH-mode DACK/DRACK to high active output, V832-mode DMAAK to high active, and V832-mode TC to low active.
8.5 SH3 Mode
(1) When the RDY pin is low, it is in the wait state. (2) DMA transfer in the single-address mode is not supported. (3) DMA transfer in the dual-address mode supports the direct address transfer mode, but does not support the indirect address transfer mode. (4) 16-byte DMA transfer in the dual-address mode is not supported. (5) The INT signal is low active.
170
8.6 SH4 Mode
(1) When the RDY pin is low, it is in the ready state. (2) At DMA transfer in the single-address mode, transfer from the main memory (SH-mode memory) to FIFO of the MB86290A can be performed, but transfer from the MB86290A to the main memory cannot be performed. (3) DMA transfer in the single-address mode is performed in units of 32 bits or 32 bytes. (4) SH4-mode 32-byte DMA transfer in the dual-address mode supports inter-memory transfer, but does not support transfer from memory to FIFO. (5) The INT signal is low active.
8.7 V832 Mode
(1) (2) (3) (4) When the RDY pin is low, it is in the ready state. Set the active level of DMAAK to high-active in V832 mode. DMA transfer supports the single transfer mode and demand transfer mode. The INT signal is high-active. Set the V832-mode registers to high-level trigger.
8.8 DMA Transfer Modes Supported by SH3, SH4, and V832
Table 8-1 Table of DMA Transfer Modes supported by SH3, SH4, and V832
Single-address mode SH3 SH 3 does not support the singleaddress mode. Dual-address mode SH3 supports the direct address transfer mode; it does not support the indirect address transfer mode. Transfer is performed in 32-bit units. SH3 supports the cycle steal mode and burst mode.
SH4
Transfer is performed in units of 32 bits or 32 bytes. SH4 supports the cycle steal mode and burst mode.
Transfer is performed in 32-bit units. Transfer to memory is performed in 32-byte units. SH4 supports transfer to FIFO. SH4 supports the cycle steal mode and burst mode. Transfer is performed in 32-bit units. V832 supports the single transfer mode and demand transfer mode.
V832
172
9 Electrical Characteristics (Preliminary Target Specifications)
9.1 Absolute Maximum Ratings
Maximum Ratings Parameter Supply voltage Input voltage Output current Power current Ambient temperature Storage temperature Symbol *1 VDDL VDDH VI *2 VIV IO IPOW TOP TST Maximum Rating -0.5 < VDDL < 3.0 -0.5 < VDDH < 4.0 -0.5 < VI < VDDH+0.5 (<4.0) -0.5 < VI < VDDH+4.0 (<6.0) +13 / -13 60 0 < TOP < 70 *3 (-40 < TOP < 85) -55 < TST < +125 Unit V V mA mA C C
*1 *2 *3
Includes analog power supply and PLL power supply HSYNC, VSYNC, EO input Temperature extended version
173
9.2 Recommended Operating Conditions
9.2.1 Recommended Operating Conditions
Recommended Operating Conditions Parameter Supply voltage Input Input high low voltage voltage Symbol VDDL VDDH VIH *2 VIHV VIL *2 VILV VREF RVRO RAOUT CACOMP TOP
*1
Input voltage to VREF VRO External resistance *3 AOUT External resistance *4 ACOMP External capacitance Ambient temperature
*1 *2 *3 *4
Min. 2.3 3.0 2.0 2.0 -0.3 -0.3 1.05
Specifications Typ. 2.5 3.3
1.10 2.7 75 0.1
Max. 2.7 3.6 VDDH+0.3 5.5 0.8 0.8 1.15
Unit V V V V k* * F C
0
70
Includes analog power supply and PLL power supply HSYNC, VSYNC, EO input AOUTR, AOUTG, AOUTB pins ACOMPR, ACOMPG, ACOMPB pins
Parameter Supply voltage Ambient Others temperature
Symbol VDDL VDDH TA T
*1
Min. 2.6 3.5 -40
Specifications Typ. 2.5 3.3
Max. 2.7 3.6 7.0
Unit V C
9.2.2 Power-on Precautions
There is no restriction on the order of power-on/power-off between VDDL and VDDH. However, do not supply only VDDH for more than a few seconds. Do not supply HSYNC, VSYNC and EC signals while the voltage supply is OFF. (See the recommended input voltage in the section on absolute maximum ratings.) After power-on, hold the S input at the `L' level for at least 500 ns. Then, after setting the S-input to the `H' level, hold the XRESET input at the `L' level for at least 300 s.
173
9.3 DC Characteristics
Condition: VDDL = 2.5 70C
0.2 V, VDDH = 3.3 0.3 V, VSS = 0.0 V, Ta = 0-
Parameter Output high voltage Output low voltage
*1
Symbol VOH VOL *3 IOH1 *4 IOH2 *5 IOH3 *3 IOL1 *4 IOL2 *5 IOL3
*6
*2
Output high current
Output low current AOUT Output current Full scale Zero scale *7 AOUT Voltage Input leakage current Load capacitance
Min. VDDH0.2 0.0 -2.0 -4.0 -8.0 2.0 4.0 8.0 9.90 0 -0.1
Specifications Typ. Max. VDDH 0.2 V V
Unit
mA
mA
IAOUT VAOUT IL C
10.42 2
10.94 20 1.1 +5/-5 16
mA A V A pF
*1 IOH = -100 A *2 IOL = 100 A *3 Output current of MD0-63, MDQM0-7 *4 Output current of all signals except *3 and *5 (not including analog signals) *5 Output current of MCLKO *6 Output current of AOUTR, AOUTG and AOUTB (VREF = 1.10 V, RVRO = 2.7 k) (The formula for full-scale output current calculation is (VREF/RVRO) x 25.575.) *7 AOUTR, AOUTG and AOUTB pins
174
9.4 AC Characteristics
9.4.1 Host Interface
Clock
Parameter BCLKI Frequency BCLKI H-width BCLKI L-width Symbol fBCLKI tHBCLKI tLBCLKI Condition Min. 1 1 Specifications Typ. Max. 100 Unit MHz ns ns
Host interface signals
Parameter Address set up time Address hold time BS Set up time BS Hold time CS Set up time CS Hold time RD Set up time RD Hold time WE Set up time WE Hold time Write data set up time Write data hold time DTACK Set up time DTACK Hold time DRACK Set up time DRACK Hold time Read data delay time (for XRD) Read data delay time RDY Delay time (for XCS) SH RDY Delay time (for XCS) V832 RDY Delay time INT Delay time DREQ Delay time MODE Hold time Symbol tADS tADH tBSS tBSH tCSS tCSH tRDS tRDH tWES tWEH tWDS tWDH tDAKS tDAKH tDRKS tDRKH tRDDZ tRDD tRDYDZ tRDYDZ tRDYD tINTD tDQRD tMODH Condition Min. 3.0 1.0 3.5 0.0 3.5 0.0 3.0 1.0 3.0 1.0 5.0 1.0 3.0 1.0 3.0 1.0 4.0 4.0 3.0 3.0 3.5 3.5 Specifications Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
*1
8.5 9.5 9.0 8.5 7 10 7 20
*1 Hold time requirement for RESET release
175
9.4.2 Video Interface
Clock
Parameter CLK Frequency CLK H-width CLK L-width DCLKI Frequency DCLKI H-width DCLKI L-width DCLKO frequency Symbol fCLK tHCLK tLCLK fDCLKI tHDCLKI tLDCLKI fDCLKO Condition Min. 25 25 67 5 5 67 Specifications Typ. 14.32 Max. Unit MHz ns ns MHz ns ns MHz
Input signals
Parameter HSYNC Input pulse width HSYNC Input set up time HSYNC Input hold time VSYNC Input pulse width EO Input set up time EO Input hold time Symbol tWHSYNC0 tWHSYNC1 tSHSYNC tHHSYNC tWHSYNC1 tSEO tHEO *3 *3 Condition *1 *2 *2 *2 Min. 3 3 10 10 1 10 10 Specifications Typ. Max. Unit clock clock ns ns
HSYNC period
ns ns
*1 In PLL synchronization mode (CKS = 0), base clock output from internal PLL (period = 1/14*fCLK) *2 In DCLKI synchronization mode (CKS = 1), base clock = DCLKI *3 For VSYNC negation edge
Output signals
Parameter EO Output delay time HSYNC Output delay time VSYNC Output delay time CSYNC Output delay time GV Output delay time Symbol tDEO tDHSYNC tDVSYNC tDCSYNC tDGV Condition *4 Min. Specifications Typ. Max. 10 10 10 10 10 Unit ns ns ns ns ns
*4 EO output changes at timing of VSYNC assertion
176
9.4.3 Graphics Memory Interface
Clock
Parameter MCLKO Frequency MCLKO H-pulse width MCLKO L-pulse width MCLKI Delay MCLKI H-Frequency MCLKI H-pulse width Symbol tMCLKO tHMCLKO tLMCLKO tDMCLKI tHMCLKI tLMCLKI tOID Condition Min. 1 1 100 1 1 1 Specifications Typ. Max. 100 Unit ns ns ns MHz ns ns ns
4
Input/Output signals
Parameter MA, MRAS, MCAS, MWE, CKE Setup time MA, MRAS, MCAS, MWE, CKE Hold time MDQM Data setup time MDQM Data hold time MD Output data setup time MD Output data hold time MD Input data setup time MD Input data hold time *1: Setup hold time for MCLKO *2: Setup hold time for MCLKI Symbol tMADS tMADH tMDQMDS tMDQMDH tMDODS tMDODH tMDIDS tMDIDH Condition *1 *1 *1 *1 *1 *1 *2 *2 Min. 3.5 1 3.5 1 3.5 1 3 1 Specifications Typ. Max. Unit ns ns ns ns ns ns ns ns
9.4.4 PLL Specifications
Parameter Input frequency (typ.) Output frequency Duty ratio Jitter
Specifications 14.31818 MHz 200.45452 MHz 101.3~93.1% 180~-150ps
Description x 14 H/L Pulse width ratio of PLL output Frequency tolerant of two consecutive clock cycles
177
9.5 Timing Diagram
9.5.1 Host Interface
Clock
1/fBCLKI tHBCLKI BCLKI tLBCLKI
Input signal setup/hold times
BCLKI
A, BS, CS, RD, WE, D, DTACK, DRACK tADS, tBSS, tCSS, tRDS, tWES, tWDS, tDAKS, tDRK tADH, tBSH, tCSH, tRDH, tWEH, tWDH, tDAKH, tDRK
178
DREQ output delay times
BCLKI
DREQ (output)
tDRQD, tINTD
RDY Delay (for CS)
BCLKI
CS
Hi-Z RDY (output) tRDYDZ tRDYDZ
Hi-Z
179
RDY, D Output delay
BCLKI
RD tRDDZ tRDD D (output) Output data Hi-Z
RDY tRDYD tRDYD
MODE Signal hold time
RESET
MODE
tMODH
180
9.5.2 Video Interface
Clock
1/fCLK tHCLK CLK VIH VIL tLCLK
HSYNC Signal setup/hold
1/fDCLKI tHDCLKI DCLKI tLDCLKI
HSYNC (input)
tSHSYNC tHHSYNC
EO Signal setup/hold
VSYNC
EO (input) tSEO tHEO
181
Output signal delay
DCLKO
EO (output) HSYNC (output) VSYNC (output) CSYNC GV tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV
182
9.5.3 Graphics Memory Interface
Clock
tMCLKO tHMCLKO MCLKO tLMCLKO
Input signal setup/hold times
MCLKI
MD0-63
tSMD
tHMD
183
MCLKI Signal delay
MCLKO
MCLKI
tDMCLKI
Output signal delay
MCLKO
MA, MRAS, MCAS, MWE, CKE, MD, MDQM
tMADS,tMDODS,tMDQMDS
tMADH,tMDODH,tMDQMDH
184

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